Bandwidth limitations of Holoscan Sensor Bridge for high-throughput sensor data (≈100 Gbps)

Robotics & Edge Computing Jetson Systems Jetson Thor
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Hello,

I’m evaluating the use of Holoscan Sensor Bridge to transfer data from multiple sensors with an aggregate throughput around 100 Gbps directly into a Jetson AGX Thor via GPU Remote DMA (RDMA). The idea is for the GPU to access the sensor data without CPU intervention.

Before moving ahead, I have a few questions:

  1. Are there known bandwidth limitations or bottlenecks in the Holoscan Sensor Bridge IP that might prevent sustaining ~100 Gbps?

  2. What hardware interfaces or architectural constraints (e.g. PCIe lanes, memory controllers, backpressure handling) should I be aware of to make such a system work reliably?

In addition, I’ve looked into FPGA partners of NVIDIA (e.g. Lattice, Microsemi).
3. Is the Holoscan Sensor Bridge IP intended only for those FPGA families, or can it be implemented on other FPGA vendors (e.g. AMD or older Altera/Intel FPGAs)?
4. I noticed an evaluation board by Terasic based on Stratix 10 (link: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1340). But I haven’t found implementations or boards using AMD FPGAs.

  • Is there a compatibility reason or technical constraint that limits support to certain FPGA vendors?

  • Are there vendor-specific dependencies (e.g. custom DSP slices, proprietary interfaces) in the IP that would prevent porting?

Any insights, references, or experiences would be highly appreciated. Thank you in advance!

3

hello marco.righetto,

>> Q1
per data bandwidth, Lattice/Microchip reference board they’re having 2x10GbE.
in theory, it support up-to 2x100GbE, however, there’s no reference board yet.

>> Q2
HSB it’s sensor-to-ethernet streaming platform, which designed for low-latency sensor data process using GPUs.
it leverage technology (RDMA/CoE) with MGBE hardware for CPU offloading and network acceleration.

>> Q3
it can be implemented on other FPGA vendors.

>> Q4
per product page, it looks it supports 2x100GbE bandwidth, which is within the theoretical value.

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Concerning Q3:

I tried integrating the Hololink IP by downloading the latest tag from GitHub
(https://github.com/nvidia-holoscan/holoscan-sensor-bridge/archive/refs/tags/2.3.1.zip)
and synthesizing the HOLOLINK_top module in Vivado.

However, the environment could not find the configuration file HOLOLINK_def.svh.
I located a copy of this file in the example projects available at
https://github.com/nvidia-holoscan/holoscan-sensor-bridge.
After adding it to the project and setting the vendor field to "XILINX", Vivado proceeds with synthesis but stops with the following message:

ERROR: [Synth 8-5809] Error generated from encrypted envelope

Since the source files are encrypted, it’s not possible to identify the root cause.
I assume that some customization of HOLOLINK_def.svh might be required, but without visibility into the encrypted files, it’s difficult to determine what needs to be changed.

This seems to limit the ability to integrate the IP into a custom FPGA platform.
Could you please provide guidance on how to properly configure the Hololink IP for Xilinx devices, or share any additional documentation for adapting it to non-reference designs?

Thank you in advance for your help.

7

Hello Marco,

I’m running into the same problem with Quartus.

Did you ever resolve your issue?

JS