Holoscan Sensor Bridge Supporting Thor 25GigE

Good day,

are there any plans to upgrade the Holoscan sensor bridge hardware to utilize the 4x25GigE networking offered by the upcoming Jetson Thor. Currently, the sensor bridge reference implementation from Lattice and Microchip only offers 10GigE.
Would the Holoscan FPGA IP support these higher bandwidths?
Also, is it possible to aggregate multiple lower bandwidth sensors/cameras per network link, similar to the virtual camera interface feature?

BR,
Dominik

Hi,N
Please share which Jetson platform you are using, so that we can suggest next. This topic is in Jetson Nano category. We don’t support Holoscan Sensor Bridge on this platform.

Thank you for the hint. I have updated tag to AGX Orin platform.

@DaneLLL I have updated the platform information. Can you please suggest next as stated?

Hi,

Currently there is no plane to change it from 10G to 25G

We have the example of running dual IMX274 on AGX Orin developer kit:
holoscan-sensor-bridge/examples/linux_single_network_stereo_imx274_player.py at main · nvidia-holoscan/holoscan-sensor-bridge · GitHub
Running Holoscan Sensor Bridge examples - NVIDIA Docs

You may take a look and give it a try.

Hi Domn,

We don’t have a plan to build a 25G HSB evalkit, and we will not have a evalkits to cover all ethernet speed grade.. However, HSB is a highly configurable IP, our holoscan sensor bridge partners have a roadmap 25G solution they are working on. Please contact Lattice and Microchip for the 25G solution. Thank you.

mark.hoopes@latticesemi.com
diptesh.nandi@microchip.com

Regards,
John

2 Likes

Thank you John!

Will reach out to the gentleman from Lattice and Microchip.

BR,
Dominik

Dear @wjohn @DaneLLL one more question:

Does Jetson Thor support ConnectX SmartNIC or similiar technology to stream directly to memory?
If one streams sensor with full 25G bandwidth it might otherwise occupy a lot of the precious CPU resource.

BR,
Dominik

Hi Domn,

Thor has 4x25G capability and comes with offload engine for GPU direct memory transaction. There will be little to no CPU utilization using HSB for data transfer.

Regards,
John

1 Like

Great! Thank you for confirming.

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