we have tested PCIE transfer bandwidth between TX2 & FPGA (soldered on the same PCB),
FPGA forms consecutive MWr(32 bit bus addressing, i.e., 3DW TLP header) TLPs, with 128B payload
(since Max_Payload_Size supported by TX2 is just 128B, that is te maximal payload size for a MWr TLP),
but we have observed long duration of ‘bus-busy’ state,
(during this state, no data can be transfered since TX2 throttles
the PCIE logic inside the FPGA)
so, just as expected, the actual speed for PCIE between FPGA & TX2 is only 658MB/s (much too lower than expected !!!).
when the same ‘FPGA & firmware’ works with x86 CPU, the measured bandwidth is: 2GB/s.
What causes the difference between the actual PCIE bandwidth between ‘TX2+FPGA’ & ‘x86+FPGA’
note that, the theoretical bandwidth for PCIE Gen2 x4 (both ‘TX2+FPGA’ & ‘x86+FPGA’ are tested in such
configuration: Gen2 x4), is 2.5GB/s, (consider the 64/66B coding effect in PCS layer, the peak bandwidth for
PCIE Gen2 x4 is 2.5 × 64 ÷ 66 = 2.42GB/s）
why does TX2 behaves so poor in PCIE bandwidth test ?
lpddr4 works at 1600MHz (or 1866MHz ??), i guess this does not make the bottleneck…
does it have anything to do with the PCIE controller ? or anything else ?