Camera don't work on xziver with Jetpack-5.0.1: YUV422-8bit, UYVY

[bwp2012]

camera:
YUV422-8bit, UYVY, 1920*1280, csi2-4 lanes

I have a camera with isp , which works fine on Jetpack-4.4.1. The interface is FPD-link. So my configure in device tree works OK.

Now I need to upgrade the system to Jetpack-5.0.1-DP and I recompile the kernel modules of camera driver, but the camera can’t work.

when I change the configure about pix_clk_hz as follow:

pix_clk_hz = "74250000"; 
serdes_pix_clk_hz = "100000000";

the debug com output:

[ 117.399165] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 131072 
[ 117.432499] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 131072 
[ 117.465832] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 131072

pix_clk_hz = "74250000"; 
serdes_pix_clk_hz = "74250000";

[ 118.904410] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 512 
[ 119.104421] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 512 
[ 119.137650] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 512

the picture from cheese:

the strange thing is that the camera can work when I use these commands which I get in other topics.

echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked

some debug info:

root@nvidia:~# cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
998400000
root@nvidia:~# cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/isp/rate
1190400000
root@nvidia:~# cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
400000000
root@nvidia:~# cat /sys/kernel/debug/bpmp/debug/clk/emc/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/emc/rate
2133000000

[ShaneCCC]

Have a try serdes_pix_clk_hz = “370000000”;

[bwp2012]

Thanks，it can work. But I have a little confusion about this value.
the guide:

serdes_pix_clk_hz = (deserializer output data rate in hertz) * (number of CSI lanes) / (bits per pixel).

370000000 = 1,480Mhz *4 lanes /16
so:
(deserializer output data rate in hertz) =1480Mhz

but I set the deserializer to 1600Mhz, I used to try this value, the error info is:

[   85.992730] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[   85.993930] (NULL device *): vi_capture_control_message: NULL VI channel received
[   85.994123] t194-nvcsi 13e10000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=2, csi_port=2
[   85.994347] (NULL device *): vi_capture_control_message: NULL VI channel received
[   85.994491] t194-nvcsi 13e10000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 2 vc- 0
[   85.995043] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[   89.607823] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[   89.608145] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[   89.609555] (NULL device *): vi_capture_control_message: NULL VI channel received
[   89.609795] t194-nvcsi 13e10000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=2, csi_port=2
[   89.610008] (NULL device *): vi_capture_control_message: NULL VI channel received
[   89.610199] t194-nvcsi 13e10000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 2 vc- 0
[   89.611010] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel

[ShaneCCC]

Could be the data rate must > 1.5G
Below is from programing guide.

SerDes Pixel Clock

For sensor modules that use serializer/deserializer chips (GMSL or FPD link), the frames received by the SoC are output from SerDes and not from the sensors. Therefore, the SerDes pixel clock must be specified correctly to configure the SoC-camera interface correctly and avoid buffer overrun issues.

You can start by checking the deserializer output data rate and ensure it is sufficient to stream all the connected sensors. After you determine the proper data rate, the SerDes pixel clock can be calculated by using the following equation:

• serdes_pix_clk_hz = (deserializer output data rate in hertz) * (number of CSI lanes) / (bits per pixel).

Note

Skew calibration is required if sensor or deserializer is using DPHY, and the output data rate is > 1.5Gbps.

An initiation deskew signal should be sent by sensor or deserializer to perform the skew calibration. If the deskew signals is not sent, the receiver will stall, and the capture will time out.

You can calculate the output data rate with the following equation:

• Output data rate = (sensor or deserializer pixel clock in hertz) * (bits per pixel) / (number of CSI lanes)