Hi,
HW:
4 cameras ====> max96712 ====>Xavier
camera: 2x 2880x1860@30fps yuv422-8bit, 2x 1280x720@30fps yuv422-8bit
max96712 output: 2000Mbps 4-lane with continuous clock
For the same GMSL register settings, camera data goes into both modules at the same time, one is Jetpack 4.4, another is Jetpack5.0.2. it works fine on Jetpack 4.4, but always bad on Jetpack5.0.2.
When I use v4l2-ctl utils to get frames, if this timeit is works fine, then it will always work fine until I terminate it with the “Ctrl+C”. When I run this command second,it will most likely go wrong. Of course, maybe a third time to run it will be fine.
mode setting with device tree:
phy_mode = “DPHY”;
serdes_pix_clk_hz = “500000000”;
discontinuous_clk = “no”
trace log:
v4l2-ctl-3197 [000] .... 2657.023476: tegra_channel_open: vi-output, imx490 1-0031
v4l2-ctl-3197 [000] .... 2657.036089: tegra_channel_set_power: imx490 1-0031 : 0x1
v4l2-ctl-3197 [000] .... 2657.036107: camera_common_s_power: status : 0x1
v4l2-ctl-3197 [000] .... 2657.036521: tegra_channel_set_power: 13e10000.host1x:nvcsi@15a00000- : 0x1
v4l2-ctl-3197 [000] .... 2657.036524: csi_s_power: enable : 0x1
v4l2-ctl-3197 [000] .... 2657.036643: tegra_channel_capture_setup: vnc_id 0 W 2880 H 1860 fmt 13
kworker/1:2-3036 [001] .... 2657.040211: rtcpu_string: tstamp:83762135057 id:0x04010000 str:"VM0 activating."
v4l2-ctl-3197 [001] .... 2657.045091: tegra_channel_set_stream: enable : 0x1
v4l2-ctl-3197 [001] .... 2657.046134: tegra_channel_set_stream: 13e10000.host1x:nvcsi@15a00000- : 0x1
v4l2-ctl-3197 [001] .... 2657.046138: csi_s_stream: enable : 0x1
v4l2-ctl-3197 [001] .... 2657.046538: tegra_channel_set_stream: imx490 1-0031 : 0x1
kworker/1:2-3036 [001] .... 2657.096204: rtcpu_vinotify_event: tstamp:83762607963 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:2680394004160 data:0xcd9ce50010000000
kworker/1:2-3036 [001] .... 2657.096206: rtcpu_vinotify_event: tstamp:83762608151 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:2680394009952 data:0x0000000031000001
kworker/1:2-3036 [001] .... 2657.096207: rtcpu_vinotify_event: tstamp:83762608343 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:2680394072576 data:0xcd9ce20010000000
kworker/1:2-3036 [001] .... 2657.096207: rtcpu_vinotify_event: tstamp:83762608506 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:2680394078144 data:0x0000000031000002
vi-output, imx4-3199 [001] .... 2659.554073: tegra_channel_capture_setup: vnc_id 0 W 2880 H 1860 fmt 13
kworker/1:2-3036 [001] .... 2659.564222: rtcpu_vinotify_event: tstamp:83840858838 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:2682903243648 data:0xcd9ce50010000000
kworker/1:2-3036 [001] .... 2659.564226: rtcpu_vinotify_event: tstamp:83840859009 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:2682903249472 data:0x0000000031000001
kworker/1:2-3036 [001] .... 2659.564227: rtcpu_vinotify_event: tstamp:83840859200 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:2682903307936 data:0xcd9ce20010000000
kworker/1:2-3036 [001] .... 2659.564227: rtcpu_vinotify_event: tstamp:83840859367 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:2682903313504 data:0x0000000031000002
thanks.