I am implementing a new driver for a new sensor.
I get the follwoing error in dmesg:
[ 708.774818] tegra194-vi5 15c10000.vi: no reply from camera processor
[ 708.776198] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[ 708.777449] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[ 708.797590] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channe
Now I am wondering if it happens because the sensor streams 1782Mbit/s, which is more than the magic 1500Mbit with CSI. Before we only had sensor below 1000Mbit/s, but the XAVIER NX should support up to 2500MBit/s.
Are there any changes I have to make to support this?
I also set line_length and pix_clk_hz higher than the calculated values in ():
may I also know which Jetpack release version you’re working with.
please check the release tag for confirmation, i.e. $ cat /etc/nv_tegra_release
your tracing logs show PHY interrupts, for instance, PHY_INTR0 phy:2 cil:1 st:0 vc:0 status:0x00000060
the error code 0x60 it means there’re bit error detected on data-lane, which usually due to the erroneous packets on CSI channel.
please note that, if that’s a case. skew calibration is required if sensor or deserializer is using DPHY, and the output data rate is > 1.5Gbps.
please note that, if that’s a case. skew calibration is required if sensor or deserializer is using DPHY, and the output data rate is > 1.5Gbps.
Can you hint me a little bit more about what skew calibration actually and how to do it with jetson? I didnt need to do it yet since it always worked instantly with <1.5Gbps.
your tracing logs show PHY interrupts, for instance, PHY_INTR0 phy:2 cil:1 st:0 vc:0 status:0x00000060
the error code 0x60 it means there’re bit error detected on data-lane, which usually due to the erroneous packets on CSI channel.
Does that mean Skew calibration is already happening and worked?
it should not deskew issue since JP-4.6 software flow it doesn’t check deskew signaling.
you may expect there’re signaling on the CSI channel, but erroneous packets. it’s suggest to send a reset signal before s_stream for verificaiton.
yes, there’re error reported by PHY_INTR0, you may also check TRM for NVCSI_PHY_0_CILA_INTR_0_MASK_CILA_0.
furthermore,
SOT_SB: it means there’s one bit error detected on the data-lane sync word
SOT_MB: it means more than one bit error has detected on the data-lane sync word.
in my experience, this usually due to sensor side did not output frames correctly.
please also review your pixel clock settings,
FYI, I usually use below formula to calculate sensor pixel clock for sensor bring-up. pixel_clk_hz = sensor data rate per lane (Mbps) * number of lanes / bits per pixel
besides, here’s see-also Topic 260685 for your reference.
no.
sorry for misunderstanding,
CSI it supports all data-rates (up-to 2.5-Gbps per lane), skew calibration is extra required only when the output data-rate is > 1.5Gbps.