Enable the orin nano spi2, and it already can output data, but can not change the SPI2 CLK frequency.
self.spi = spidev.SpiDev() self.spi.open(2, 0) self.spi.mode = SPI_MODE self.spi.max_speed_hz = 80000
Event setup those config, SPI still output 150Khz CLK.
Hi HeapCorrupt,
Are you using the devkit or custom board for Orin Nano?
What’s your Jetpack version in use?
Could you share the SPI configuration in device tree?
Hi @KevinFFF
devkit board for orin nano 4gb， use spi2 form header 40 pin(13,16,18,22,37), use jetson-gpio to control the spi interface.
R35.4.1
spi@3230000 {
compatible = “nvidia,tegra186-spi”;
reg = <0x00 0x3230000 0x00 0x10000>;
interrupts = <0x00 0x26 0x04>;
#address-cells = <0x01>;
#size-cells = <0x00>;
iommus = <0x06 0x04>;
dma-coherent;
dmas = <0x3f 0x11 0x3f 0x11>;
dma-names = “rx\0tx”;
spi-max-frequency = <0x3dfd240>;
nvidia,clk-parents = “pll_p\0clk_m”;
clocks = <0x02 0x89 0x02 0x66 0x02 0x0e>;
clock-names = “spi\0pll_p\0clk_m”;
resets = <0x02 0x5d>;
reset-names = “spi”;
status = “okay”;
phandle = <0x314>;
prod-settings {
#prod-cells = <0x04>;
prod {
prod = <0x00 0x194 0x80000000 0x00>;
};
};
spi@0 {
compatible = "tegra-spidev";
reg = <0x00>;
spi-max-frequency = <0x2faf080>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x00>;
};
};
spi@1 {
compatible = "tegra-spidev";
reg = <0x01>;
spi-max-frequency = <0x2faf080>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x00>;
};
};
};
PLEASE help me to check this issue.
How did you get 150KHz CLK?
Is that measured from Oscilloscope?
Have you tried to configure spi-max-frequency in device tree?
Which device are you using? (on CS0 or CS1)
Hi @KevinFFF
logic analyzer:
No, spi-max-frequency = <0x03 0xDF 0xD2 0x40>;
SPI2.0, CS0
import spidev
import time
# 初始化 SPI 设备
spi = spidev.SpiDev()
# 打开 SPI2，CE0（Chip Enable 0）
spi.open(2, 0)
# 配置 SPI
spi.mode = 0b11 # 使用模式 3
spi.max_speed_hz = 80000 # 设置速度为 80KHz
try:
# 发送数据 到 SPI 设备
sent_data = [0x0a, 0x00, 0x0a, 0x00]
print(f"发送的数据： {sent_data}")
# xfer2 方法用于发送然后接收数据
received_data = spi.xfer2(sent_data)
print(f"接收的数据： {received_data}")
time.sleep(0.01)
except KeyboardInterrupt:
print("结束 SPI 通信")
finally:
spi.close() # 关闭 SPI 设备
It is strange that this spi clk frequency can only be increased but not decreased. For example, the clk configuration is not available if it is lower than 150khz, but it is available if it is higher than 150khz, for example, it can be configured as 200khz.
I can not config the SPI2’s CLK to low frequency, like 80khz. seems it need to config the SPI clock source ? How to do it?
Do you mean it would work if you configure it higher than 150000 but it would not work if you configure it less than 150000?
What’s your use case for 80KHz? Is that the limitation from your SPI device?
For lower SPI frequncy, you may need to use another parent clock for SPI2.
Please refer to the following steps:
Step 1. Check current parent clock
$ sudo su
# cat /sys/kernel/debug/bpmp/debug/clk/spi2/parent
pllp_out0
Step 2. Use pll_c instead
# echo pll_c > /sys/kernel/debug/bpmp/debug/clk/spi2/parent
Step 3. Check its rate
# cat /sys/kernel/debug/bpmp/debug/clk/spi2/rate
Step 4. Check if SPI2 could work with 80KHz in your case
Hi @KevinFFF
Oddly, the above steps are executed correctly, but the SPI2 clock outpu is still 150khz. Could you reproduce this problem in your side?
Sorry that I don’t have the oscilloscope currently.
Could you also try with another clock in Step 2?
# echo osc > /sys/kernel/debug/bpmp/debug/clk/spi2/parent
or
# pll_aon > /sys/kernel/debug/bpmp/debug/clk/spi2/parent
or
# clk_32k > /sys/kernel/debug/bpmp/debug/clk/spi2/parent
No, that won’t works for me.
I’ve checked this with internal.
The minimum supported frequency for SPI is 300kHz, which is derived from CLK_M (38.4MHz)/ (128.5) = ~298kHz
Please verify with the 300kHz.
Oh, sadly, will check other solution.
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