Capturing Image from custom sensor fails with 4-csi lanes

Hi,

we use a NVIDIA Jetson Orin NX System to capture images of a custom mipi-csi cam. We already verified, that our camera works correctly on a non nvidia system with 2 and 4 lanes.
If we use a 2 lane configuration, everything works as expected. We can successfully capture an image via v4l.

If we use 4 mipi lanes on CSI-Port 0. No image can be acquired anymore.

Platform:

DeviceTree:
DeviceTree.txt (5.3 KB)

Logs:
log_2_lanes_successfull.txt (28.1 KB)
log_4_lanes_error.txt (11.6 KB)

Could you please check our settings?

Thanks

ToHo

hello toho,

is it a customize carrier board, or Orin NX DevKit?
FYI,
please refer to Jetson Orin Nano Developer Kit Carrier Board Specification for the [3.2 Camera Connector], the connectors support the following.

J20: CSI 1 x2 lane
J21: CSI 1 x2 lane or 1 x4 lane

Hi @JerryChang, @toho uses the Boson carrier board from Connect Tech. We are working together on this Problem.

This should support 4x2 (connector cam 1-4) or 2x4 (connector cam1 and cam2).
Do you see any mistake in our device Tree regarding this switch from 4x2 to 2x4? We simply use the defines on top to change this setting.

	#define CAM_LANES 2
	#define CAM_LANES_STRING "2"

hello aaron2222,

please note that, Orin NX/Nano has CSI0 D1 and CSI1 D0 P/N will always been swizzled for P/N.
please use device tree property, lane_polarity to configure a polarity swap on any lane.

Hi @JerryChang, as you can see in the device-tree attached in the first post - we already have:
lane_polarity = “6”;
Or is there a mistake?
Do you have any other hints?

hello aaron2222,

you may double check Sensor Pixel Clock section.
for instance, pix_clk_hz = sensor data rate per lane (Mbps) * number of lanes / bits per pixel
in general, if this is pix_clk_hz = "74250000"; for 2-lane, you should multiply pixel clock by two for 4-lane configuration.

Hi @JerryChang,
thanks for your fast response. We found the Problem at another place:
The connect-tec board has 4 camera connectors, but the CSI lanes can be switches between:
Cam 1: CSI0 (2-lane)
Cam 2: CSI1 (2-lane)
Cam 3: CSI2 (2-lane)
Cam 4: CSI3 (2-lane)
and
Cam 1: CSI0/CSI1 (4-lane)
Cam 2: CSI2/CSI3 (4-lane)

This has to be done in the device-tree via a separate Multiplexer on i2c.
With the support of connect-tec we got some examples to set it corret. It is missing in the public documentation.

hello aaron2222,

it should be port-index mapping for those CSI bricks.
I’m not fully understand what you’ve done to address the issue, could you please share the code snippets for quick checking.

Hi JerryChang,
the problem was hardware related, the carrierboard has an undocumented mipi switch which has to be enabled for using 4 lanes-mipi.
Thanks for your help

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