Hello all,
I’m currently running a bare-metal application on the TX1 and I would like to use the Watchdog Timers provided by NVIDIA.
I used the Technical Reference Manual v1.1p and configured the TIMER_WDT_CONFIG_0 and TIMER_WDT_COMMAND_0 registers to reset all cores after the counter expires for the third time.
Nothing happens and the TIMER_WDT_STATUS_0 returns 0x11, meaning the watchdog is indeed enabled with a reload value of 1us (as I specified). However it seems the timer does not start as the count of expiration is still zero.
So here are my questions :
I asssigned the TMR1 to the watchdog, do I need to configure the PCR and PTV registers?
Do you have some examples of watchodg implementation? I looked at the upstream ATF which supports the TX1 and they are not using it.
If this is running under L4T then the Linux kernel already has some things set up for this. It is possible that the register you are dealing with is also being set up by the kernel. If watchdog software is already set up, you will have this file:
/dev/watchdog
The existing Linux implementation monitors whether something reads the watchdog files. If the file is opened for read, the timer runs. If something writes to the file, the timer is reset. Doing this for a short time will result in the JTX1 rebooting:
sudo tail -f /dev/watchdog
To prevent reboot you could do something like this:
sudo echo 1 > /dev/watchdog
Likewise, killing the “tail -f” would also cancel reboot.
The kernel driver for this would probably be a good template for watchdog code under Linux.
I managed to implement the watchdog and it works perfectly fine (only on one core though for now). Thanks for your assistance.
Hi,Pierre_Lucas :
I want to implement the watchdog. Can you tell me how I should operate?