Creating new DTS file

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
1

Hi,

In following the process outlined in the ‘adaptation guide’ for Xavier we are instructed to modify many .dtsi files, and .cfg files in varying locations.

I have done that, but it is unclear to me how to pull those specific sources together in a new compiled dts or dtb file that can be flashed to the target.

I see the bct.mk file, and the .conf.common files, they seem to point to different locations, and i’m sure there is some script that handles all of that somewhere, but i cant locate it based on the documentation.

Is there an actual clear/useful step by step for how this is compiled into a new set of DTB and CFG files?

As reference, I have modified the following files (new extension based on our board name):

  • tegra19x-uswap_val9k-gpiopinmux-1-1.cfg (placed in bootloader/t186ref/BCT/)
  • tegra19x-mb1-pad-uswap_val9k-1-1.cfg (placed in bootloader/t186ref/BCT/)
  • tegra194-power-tree-p2888-0001-uswap_val9k-0000.dtsi (placed in /sources/hardware/nvidia/platform/t19x/galen/kernel-dts/common)
  • tegra194-fixed-regulator-uswap_val9k-0000.dtsi (placed in /sources/hardware/nvidia/platform/t19x/galen/kernel-dts/common)
  • tegra194-soc-i2c-uswap_val9k.dtsi (placed in /sources/hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc)
  • tegra194-soc-sdhci-uswap_val9k.dtsi (placed in /sources/hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc)
  • tegra194-soc-uart-uswap_val9k.dtsi (placed in /sources/hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc)
  • tegra194-soc-pcie-uswap_val9k.dtsi (placed in /sources/hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc)

I then made a copy of the p2972-0000.conf.common file, which is what jetson-xavier.conf (symbolic link to p2972-0000-devkit.conf which references that file)

So my modified p2972-0000-devkit.conf reads:

# p2972-0000-devkit.conf: configuration for T194 Silicon

# Commenting this out and replacing with uswap_val9k file names
#source "${LDK_DIR}/p2972-0000.conf.common";
#PINMUX_CONFIG="tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg";
source "${LDK_DIR}/uswap_val9k-0000.conf.common";
PINMUX_CONFIG="tegra19x-uswap_val9k-gpiopinmux-1-1.cfg";

And the conf.common referenced in this file is also modified now:

# Common values and/or defaults across p2972-0000*.conf:
# This section has been modified for uswap_val9k where appropriate

# ODMDATA is where UPHY lane mapping occurs - currently this value was set for the 2822 board
# Bits 31:27 control HSIO-PCIE-XBAR configurations for controllers 4-0 (where is controller 5?)
# Bits 24:23 control UFS configurations
# Bit 22 controls SATA 
#
#
# 2822 breakdown of settings
# 0x919 --> 0b10010 || 0b11 || 0b0 
# pcie-xbar-8-0-1-0-2 --> C5 = 8 lanes, C4 = 0 lanes, C3 = 1 lane, C1 = 0 lanes, C0 = 2 lanes?
# This doesnt align with the P2822 design...C0 should be 4 lanes for the M.2 Key M
# UFS config = Enabled, L10 and L11
# This algins with the 2822 design, L10 is for the UFS card, and L11 is for eSATA
# SATA = disabled, this must be different from the eSATA controller.
#
#
# For val9k we want the following:
# 0x280   --> b00101 || 0b00 || 0b00
# pcie-xbar-4-0-1-1-2 --> C5 = 4 lanes (Zynq), C4 = 0 lanes (unused), C3 = 1 lane (VU1), C1 = 1 lane (VU2), C0 = 2 lanes? (Should be 4, but this value is here on 2822...
# UFS config = disabled
# SATA = disabled
#
#P2822 
#ODMDATA=0x9190000;
#
#uswap_val9k
ODMDATA=0x2800000;
CHIPID=0x19;
EMMC_CFG=flash_t194_sdmmc.xml;
BOOTPARTSIZE=8388608;
EMMCSIZE=31276924928;
ITS_FILE=;
# Seems pretty generic, not going to modify
SYSBOOTFILE=p2972-0000/extlinux.conf;
# This is the BPMP DTB file (boot and power management processor), probably don't need to 
# modify this since it is the SOM and not carrier. Made a copy and re-named for best practice
#
#P2822
#BPFDTB_FILE=tegra194-a01-bpmp-p2888-a01.dtb;
#
#uswap_val9k
BPFDTB_FILE=tegra194-a02-bpmp-p2888-a04-uswap_val9k.dtb;
#P2822 
#DTB_FILE=tegra194-p2888-0001-p2822-0000.dtb;
#
#uswap_val9k
DTB_FILE=tegra194-p2888-0001-uswap_val9k-0000.dtb;
#P2822
#TBCDTB_FILE=tegra194-p2888-0001-p2822-0000.dtb;
#
#uswap_val9k
TBCDTB_FILE=tegra194-p2888-0001-uswap_val9k-0000.dtb
ROOTFSSIZE=28GiB;
# This may need to be changed to be UART3?
CMDLINE_ADD="console=ttyTCU0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 rootfstype=ext4";
target_board="t186ref";
ROOT_DEV="mmcblk0p12 ------------ internal eMMC.
        sda1 ----------------- external USB devices. (USB memory stick, HDD)
        eth0 ----------------- nfsroot via RJ45 Ethernet port.
        eth1 ----------------- nfsroot via USB Ethernet interface.";
TEGRABOOT="bootloader/nvtboot_t194.bin";
WB0BOOT="bootloader/warmboot_t194_dev.bin";
FLASHAPP="bootloader/tegraflash.py";
FLASHER="bootloader/nvtboot_recovery_cpu_t194.bin";
BOOTLOADER="bootloader/nvtboot_cpu_t194.bin";
INITRD="bootloader/l4t_initrd.img";
TBCFILE="bootloader/cboot_t194.bin";
BPFFILE="bootloader/bpmp_t194.bin";
TOSFILE="bootloader/tos_t194.img";
EKSFILE="bootloader/eks.img";
MTSPREBOOT="bootloader/preboot_c10_cr.bin";
MTS_MCE="bootloader/mce_c10_cr.bin";
MTSPROPER="bootloader/mts_c10_cr.bin";
MB1FILE="bootloader/mb1_t194_dev.bin";
SOSFILE="bootloader/mb1_t194_dev.bin";
MB2BLFILE="bootloader/nvtboot_recovery_t194.bin";
SPEFILE="bootloader/spe_t194.bin";
CAMERAFW="bootloader/camera-rtcpu-rce.img";
MB2APPLET="nvtboot_applet_t194.bin"
FBFILE="fuse_bypass_t194.xml";
CBOOTOPTION_FILE="bootloader/cbo.dtb";

# BCT args:
#
BCT="--sdram_config";
BINSARGS="--bin \"";
# Unchanged
EMMC_BCT1="tegra194-memcfg-sw-override.cfg";
# Unchanged
EMMC_BCT="tegra194-mb1-bct-memcfg-p2888.cfg";
# Unchanged
MISC_CONFIG="tegra194-mb1-bct-misc-flash.cfg";
# Unchanged
MISC_COLD_BOOT_CONFIG="tegra194-mb1-bct-misc-l4t.cfg";
# Unchanged
BOOTROM_CONFIG="tegra194-mb1-bct-reset-p2888-0000-p2822-0000.cfg";
# Unchanged
DEV_PARAMS="tegra194-br-bct-sdmmc.cfg";
# Unchanged
SCR_COLD_BOOT_CONFIG="tegra194-mb1-bct-scr-cbb-mini.cfg";
# Unchanged
SCR_CONFIG="tegra194-mb1-bct-scr-cbb-mini.cfg";
# Modified for uswap_val9k from Excel pin mux table
PINMUX_CONFIG="tegra19x-uswap_val9k-gpiopinmux-1-1.cfg";
# Unchanged
PMIC_CONFIG="tegra194-mb1-bct-pmic-p2888-0001-a01-p2822-0000.cfg";
# Modified for uswap_val9k from Excel pin mux table
PMC_CONFIG="tegra19x-mb1-pad-uswap_val9k-1-1.cfg";
# Unchanged
PROD_CONFIG="tegra19x-mb1-prod-p2888-0000-p2822-0000.cfg";
# Unchanged
BR_CMD_CONFIG="tegra194-mb1-bct-reset-p2888-0000-p2822-0000.cfg";
# Unchanged
DEVICE_CONFIG="tegra19x-mb1-bct-device-sdmmc.cfg";
# Modified for uswap_val9k, removed lane 10 assignment from file
UPHY_CONFIG="tegra194-mb1-uphy-lane-p2888-0000-uswap_val9k-0000.cfg";
# Unchanged
GPIOINT_CONFIG="tegra194-mb1-bct-gpioint-p2888-0000-p2822-0000.cfg";
# Unchanged
SOFT_FUSES="tegra194-mb1-soft-fuses-l4t.cfg";
# Unchagned
NVKEY_FILE="t194_rsa_dev.key";
# Unchanged
NVENCRYPTKEY_FILE="t194_sbk_dev.key";

# Default FAB: Force Galen boards without properly programmed EEPROM.
# Values: A01 ->
#
DEFAULT_FAB="A01";

However, I need to now compile a new .dtb file, which is referenced as the TBCDTB_FILE and the DTB_FILE

I assume that the modified dtsi files need to be pulled into the new .dtb, but there are no clear instructions there for that, and I can’t locate the list of what went into the original compilation of the dtb file that was previously referenced in the p2972-0000.conf.common file (tegra194-p2888-0001-p2822-0000.dtb)

I see the .dts file in the galen kernel location, along with a make file - but that dts file is basically empty:

/*
 * Top level DTS file for CVM:P2888-0001 and CVB:P2822-0000.
 *
 * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */
#include "common/tegra194-p2888-0001-p2822-0000-common.dtsi"
#include "common/tegra194-p2822-camera-modules.dtsi"
#include "t19x-common-modules/tegra194-camera-plugin-manager.dtsi"
  • tegra194-p2888-0001-p2822-0000-common.dtsi looks like the correct file to edit the include statements in, but that is really a guess at this point, since it's really just me poking around this huge source code archive....
  • I have no interest in the camera modules or camera-plugin-manager, we aren't using cameras on our custom carrier, I assume we can leave that as is.
#include "dt-bindings/extcon-ids.h"
#include "dt-bindings/gpio/tegra194-gpio.h"
#include "tegra194-p2888-0000-a00.dtsi"
#include <t19x-common-platforms/tegra194-platforms-eqos.dtsi>
#include "tegra194-p2822-0000-a00.dtsi"
#include "tegra194-power-tree-p2888-0001-p2822-1000.dtsi"
#include <t19x-common-platforms/tegra194-comms.dtsi>
#include "tegra194-thermal-p2888.dtsi"
#include "tegra194-plugin-manager-p2888-0000.dtsi"
#include "tegra194-plugin-manager-p2822-0000.dtsi"
#include "tegra194-super-module-e2614-p2888-0000.dtsi"

Is the above where I would replace the references to the dtsi files that I modified?

If so, then how do i re-compile the dtb properly? Just DTC the ‘top level DTS’ file (or a copy of it probably) with renamed includes etc?

Big time gap here is the user-friendliness of adapting this SoM to a custom carrier - I would really think a system like Xilinx/Altera(Intel) would go a long way to making this more adaptable and more widely used. This is really brutal.

2

So after much modification to the file chain, I cannot run the DTC tool because the ‘top level DTC’ uses #include statements - what is the suggested workflow?

3

“.dts” is a source file, “.dtsi” is just an “include” header. Include headers are only used when building device trees directly in the kernel source. Assuming you have configured the kernel correctly to match your current kernel config (perhaps with “/proc/config.gz” edited to have CONFIG_LOCALVERSION=“-tegra”), then the “make” target is “dtbs”. Within the kernel config various bits and pieces of device tree files are combined to create the device trees used in the flash.

You could just look at your flash logs from a previous flash (or look for documentation on finding the name of the “.dtb” file in the flash software), reverse compile that without bothering with the kernel source, edit, and then recompile (putting the result back into the same filename…though you’d want a backup of the original).

For example, if you find the file actually flashed from the host PC is “~/nvidia/nvidia_sdk/JetPack_4.2_Linux_P2888/Linux_for_Tegra/kernel/dtb/tegra186-quill-p3310-1000-a00-00-base.dtb” (I just picked that as an arbitrary example):

cd ~/nvidia/nvidia_sdk/JetPack_4.2_Linux_P2888/Linux_for_Tegra/kernel/dtb/
dtc -I dtb -O dts -o edit.dts tegra186-quill-p3310-1000-a00-00-base.dtb
# ...edit the file...
# ...rebuild...
dtc -I dts -O dtb -o edited.dtb edit.dts
# Save a backup first of tegra186-quill-p3310-1000-a00-00-base.dtb...
cp edited.dtb tegra186-quill-p3310-1000-a00-00-base.dtb
# Flash as usual.
4

@linuxdev - thanks as always for the response

However, I did reverse compile, and the resulting DTS didnt make much sense to me so I started following the procedure outlined by nVidia for doing this.

It seems I need to pre-process the DTS with the include files in order to follow their suggested workflow - I like the idea of modifying all of the DTSI files so that I keep changes contained and under control.

But I don’t know how to get over this last hurdle.

5

Just download the kernel source, set the config to match the running system (perhaps copy “/proc/config.gz” and set CONFIG_LOCALVERSION=“-tegra”), and test if you can build the kernel and modules (just a sanity check). If this succeeds, then you should be able to “make dtbs” (or with options such as “O=/some/where” for output location). “config.gz” would replace the “make whatever_defconfig” often described in the documentation.

In your “Linux_for_Tegra/” directory on the host is a script which is portable and can be used to download kernels for various releases. An example:

./source_sync.sh -k tegra-l4t-r32.1

(creates a “source/” subdirectory with both in-tree and out-of-tree content)

The base documentation has a kernel customization section which explains cross compiling of the kernel.

Note: You might need to add other packages, e.g., “sudo apt-get install libncurses5-dev”.

6

Thanks again.

I did do the source_sync step, and do have the huge pile of files on my Linux VM where I am doing this work.

I’ll poke around there and see if i can cross-compile it successfully.

7

source_sync.sh works on the Xavier as well if you prefer native compiling.

8

So I did modify the -2888-2822 dts file, after copying/renaming

Basically I just changed the dts filename entry

nvidia,dtsfilename = "/dvs/git/dirty/git-master_linux/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/ttegra194-p2888-0001-uswap_val9k-0000-common.dtsi";

Which points to the dtsi file i modified to include all of the changes that i wanted made based on our configuration

/*
 * Common include DTS file for uswap_val9k alion design.
 *
 * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

/*Not a real file?*/
/*#include "dt-bindings/extcon-ids.h"*/
/*Unchanged*/
#include "dt-bindings/gpio/tegra194-gpio.h"
/*This needs to be changed to pull in the i2c, sdhci, uart and pcie changes made*/
#include "tegra194-p2888-0000-a00-uswap_val9k.dtsi"
/*Unchanged*/
#include <t19x-common-platforms/tegra194-platforms-eqos.dtsi>
/*Unchanged, only oddity here may be the 'power key' entry*/
#include "tegra194-p2822-0000-a00.dtsi"
/*Changed to uswap_val9k*/
#include "tegra194-power-tree-p2888-0001-uswap_val9k-0000.dtsi"\
/*Unchanged*/
#include <t19x-common-platforms/tegra194-comms.dtsi>
/*Unchanged*/
#include "tegra194-thermal-p2888.dtsi"
/*Unchanged*/
#include "tegra194-plugin-manager-p2888-0000.dtsi"
/*Unchanged*/
#include "tegra194-plugin-manager-p2822-0000.dtsi"
/*Unchanged*/
#include "tegra194-super-module-e2614-p2888-0000.dtsi"

/ {
	nvidia,dtsfilename = __FILE__;
	nvidia,dtbbuildtime = __DATE__, __TIME__;
	nvidia,fastboot-usb-vid = <0x0955>;
	nvidia,fastboot-usb-pid = <0xee1e>;
	model = "jetson-xavier";

	compatible = "nvidia,jetson-xavier", "nvidia,tegra194";

	chosen {
		bootargs ="console=ttyTCU0,115200";
		board-has-eeprom;
	};

	firmware {
		android {
			compatible = "android,firmware";
			hardware = "jetson-xavier";
			vbmeta {
				compatible = "android,vbmeta";
				parts = "vbmeta,kernel,kernel-dtb,APP,vendor,SOS";
			};
			fstab {
				compatible = "android,fstab";
				vendor {
					compatible = "android,vendor";
					dev = "/dev/block/platform/3460000.sdhci/by-name/vendor";
					type = "ext4";
					mnt_flags = "ro";
					fsmgr_flags = "wait,avb";
				};
				odm {
					compatible = "android,odm";
					dev = "/dev/block/platform/3460000.sdhci/by-name/odm";
					type = "ext4";
					mnt_flags = "ro";
					fsmgr_flags = "wait,avb";
				};
			};
		};
	};

	spi@c260000 {
		status = "disabled";
	};

	spi@3270000 {
		status = "disabled";
	};

	spi@3300000 {
		status = "disabled";
	};

	pmc@c370000 {
		nvidia,invert-interrupt;
	};

	i2c@c240000 {
		bmi160@69 {
			compatible = "bmi,bmi160";
			reg = <0x69>;
			interrupt-parent = <&tegra_aon_gpio>;
			interrupts = <TEGRA194_AON_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
			accelerometer_matrix    = [01 00 00 00 01 00 00 00 01];
			gyroscope_matrix        = [01 00 00 00 01 00 00 00 01];
			accelerometer_delay_us_min = <1250>;
			gyroscope_delay_us_min = <1250>;
			status = "okay";
		};
		ucsi_ccg: ucsi_ccg@8 {
			status = "okay";
			typec-extcon {
				typec_port0: port-0 {
					status = "okay";
					#extcon-cells = <1>;
				};
				typec_port1: port-1 {
					status = "okay";
					#extcon-cells = <1>;
				};
			};
			typec-pd {
				typec_pd: pd {
					status = "okay";
					#extcon-cells = <1>;
				};
			};
		};
	};

#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2

	xusb_padctl: xusb_padctl@3520000 {
		status = "okay";

		pads {
			usb2 {
				lanes {
					usb2-0 {
						nvidia,function = "xusb";
						status = "okay";
					};
					usb2-1 {
						nvidia,function = "xusb";
						status = "okay";
					};
					usb2-2 {
						nvidia,function = "xusb";
						status = "okay";
					};
					usb2-3 {
						nvidia,function = "xusb";
						status = "okay";
					};
				};
			};
			usb3 {
				lanes {
					usb3-0 {
						nvidia,function = "xusb";
						status = "okay";
					};
					usb3-2 {
						nvidia,function = "xusb";
						status = "okay";
					};
					usb3-3 {
						nvidia,function = "xusb";
						status = "okay";
					};
				};
			};
		};

		ports {
			usb2-0 {
				mode = "otg";
				status = "okay";
			};
			usb2-1 {
				mode = "host";
				status = "okay";
			};
			usb2-2 {
				mode = "host";
				status = "okay";
			};
			usb2-3 {
				mode = "host";
				status = "okay";
			};
			usb3-0 {
				nvidia,usb2-companion = <1>;
				status = "okay";
			};
			usb3-2 {
				nvidia,usb2-companion = <0>;
				status = "okay";
			};
			usb3-3 {
				nvidia,usb2-companion = <3>;
				nvidia,usb3-gen1-only= <1>;
				status = "okay";
			};
		};
	};
#endif

	tegra_xudc: xudc@3550000 {
		extcon-cables = <&typec_port0 0>;
		extcon-cable-names = "vbus";
		#extcon-cells = <1>;
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
		phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>,
			<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-2}>;
		phy-names = "usb2", "usb3";
		nvidia,xusb-padctl = <&xusb_padctl>;
#endif
		nvidia,boost_cpu_freq = <1200>;
		status = "okay";
	};

	tegra_xhci: xhci@3610000 {
		extcon-cables = <&typec_port0 1>;
		extcon-cable-names = "id";
		#extcon-cells = <1>;
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
		phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>,
			<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-1}>,
			<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-3}>,
			<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-2}>,
			<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-2}>,
			<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-0}>,
			<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-3}>;
		phy-names = "usb2-0", "usb2-1", "usb2-3", "usb2-2",
			"usb3-2", "usb3-0", "usb3-3";
		nvidia,xusb-padctl = <&xusb_padctl>;
#endif
		status = "okay";
	};

	arm-pmu {
		status = "okay";
	};

	power-domain {
		status = "disabled";
	};

	interrupt-controller {
		status = "disabled";
	};

	mods-simple-bus {
		status = "disabled";
	};

	eeprom-manager {
		status = "disabled";
	};

	cpuidle {
		compatible = "nvidia,tegra19x-cpuidle";
		status = "okay";
	};

	thermal-zones {
		status = "disabled";
	};

	reserved-memory {
		ramoops_carveout {
			status = "okay";
		};
	};

	mttcan@c310000 {
		status = "okay";
	};

	mttcan@c320000 {
		status = "okay";
	};

	serial@3110000 {
		status = "okay";
	};

	pwm@32c0000 {
		status = "okay";
	};

	pwm@32f0000 {
		status = "okay";
	};

	i2c@31e0000 {
		pinctrl-names = "default";
		pinctrl-0 = <&dpaux_default>;
		bmi160@69 {
			compatible = "bmi,bmi160";
			reg = <0x69>;
			accelerometer_matrix    = [01 00 00 00 01 00 00 00 01];
			gyroscope_matrix        = [01 00 00 00 01 00 00 00 01];
			status = "okay";
		};
	};

	host1x {
		dpaux@155F0000 {
			status = "okay";
			compatible = "nvidia,tegra194-dpaux3-padctl";
			/delete-property/ power-domains;
			dpaux_default: pinmux@0 {
				dpaux3_pins {
					pins = "dpaux3-3";
					function = "i2c";
				};
			};
		};
	};

	hardwood {
		compatible = "nvidia,denver-hardwood";
		interrupts = <0 24 0x4>;
	};

	ufshci@2450000 {
		nvidia,enable-hs-mode;
	};
};

&head0 {
	extcon-cables = <&typec_port0 2 &typec_port1 2>;
	extcon-cable-names = "typec0", "typec1";
	#extcon-cells = <1>;
};

&head1 {
	extcon-cables = <&typec_port0 2 &typec_port1 2>;
	extcon-cable-names = "typec0", "typec1";
	#extcon-cells = <1>;
};

&head2 {
	extcon-cables = <&typec_port0 2 &typec_port1 2>;
	extcon-cable-names = "typec0", "typec1";
	#extcon-cells = <1>;
};

&sor0 {
	nvidia,typec-port = /bits/ 8 <0>;
};

&sor1 {
	nvidia,typec-port = /bits/ 8 <1>;
};

#if LINUX_VERSION >= 414
#include <tegra194-linux-4.14.dtsi>
#endif

And it certainly made a dtb file, after I ran:

dtc -I dts -O dtb -o test.dtb tegra194-p2888-0001-uswap_val9k-0000.dts

But I got this slew of warnings (not the full list):

test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@104 simple-bus unit address format error, expected "68"
test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@105 simple-bus unit address format error, expected "69"
test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@106 simple-bus unit address format error, expected "6a"
test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@107 simple-bus unit address format error, expected "6b"
test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@108 simple-bus unit address format error, expected "6c"
test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@109 simple-bus unit address format error, expected "6d"
test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@110 simple-bus unit address format error, expected "6e"
test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@111 simple-bus unit address format error, expected "6f"
test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@112 simple-bus unit address format error, expected "70"
test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@113 simple-bus unit address format error, expected "71"
test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@114 simple-bus unit address format error, expected "72"
test.dtb: Warning (simple_bus_reg): Node /fixed-regulators/regulator@200 simple-bus unit address format error, expected "c8"

I don’t think these are fatal…but it strikes me as odd…do I just need to modify the .dts more?

9

Also, none of my changes were pulled in from all the modifications that I made to the underlying files.

p2822_vdd_3v3_cvb = "/fixed-regulators/regulator@101";
		p2822_vdd_1v8_cvb = "/fixed-regulators/regulator@102";
		p2822_vdd_1v8_sd = "/fixed-regulators/regulator@104";
		p2822_vdd_epb_1v0 = "/fixed-regulators/regulator@105";
		p2822_vdd_sdmmc1_sw = "/fixed-regulators/regulator@106";
		p2822_avdd_cam_2v8 = "/fixed-regulators/regulator@107";
		p2822_vdd_sata_1v5 = "/fixed-regulators/regulator@108";
		p2822_vdd_1v8_slt = "/fixed-regulators/regulator@109";
		p2822_vdd_3v3_slt = "/fixed-regulators/regulator@110";
		p2822_vdd_fan = "/fixed-regulators/regulator@111";
		p2822_vdd_hdmi_5v0 = "/fixed-regulators/regulator@112";
		p2822_vdd_sys_en = "/fixed-regulators/regulator@113";
		p2822_vdd_5v_sata = "/fixed-regulators/regulator@114";
		battery_reg = "/fixed-regulators/regulator@0";
		vdd_1v8_aud2 = "/fixed-regulators/regulator@200";

Those are all gone, and replaced by:

{
	fixed-regulators {
/* LTM4686
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/	
		uswap_val9k_vcc_3v3_main: regulator@101 {
			compatible = "regulator-fixed";
			reg = <101>;
			regulator-name = "vcc-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};

		uswap_val9k_vaux_1v8: regulator@102 {
			compatible = "regulator-fixed";
			reg = <102>;
			regulator-name = "vaux-1v8";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};
/* TPS51200*/
		uswap_val9k_ddr4_vtt: regulator@104 {
			compatible = "regulator-fixed";
			reg = <104>;
			regulator-name = "ddr4-vtt";
			regulator-min-microvolt = <600000>;
			regulator-max-microvolt = <600000>;
		};

/* This is a load switch output, but is not under control of the xavier, discrete logic controls the supply rails*/		
		uswap_val9k_vccfmc_12v: regulator@105 {
			compatible = "regulator-fixed";
			reg = <105>;
			regulator-name = "vccfmc-12v";
			regulator-min-microvolt = <12000000>;
			regulator-max-microvolt = <12000000>;
		};
/* This is a load switch output, but is not under control of the xavier, discrete logic controls the supply rails*/		
		uswap_val9k_vccfmc_adj: regulator@106 {
			compatible = "regulator-fixed";
			reg = <106>;
			regulator-name = "vccfmc-adj";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};	
/* IRPS5401A
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/	
		uswap_val9k_mgtavcc_znq: regulator@107 {
			compatible = "regulator-fixed";
			reg = <107>;
			regulator-name = "mgtavcc-znq";
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <900000>;
		};
		
		uswap_val9k_vccaux_2v5: regulator@108 {
			compatible = "regulator-fixed";
			reg = <108>;
			regulator-name = "vccaux-2v5";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
		};	
			
		uswap_val9k_mgtavtt_znq: regulator@109 {
			compatible = "regulator-fixed";
			reg = <109>;
			regulator-name = "mgtavtt-znq";
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};		
	
		uswap_val9k_vccint_vcu: regulator@110 {
			compatible = "regulator-fixed";
			reg = <110>;
			regulator-name = "vccint-vcu";
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <900000>;
		};
		
		uswap_val9k_mgtravcc: regulator@111 {
			compatible = "regulator-fixed";
			reg = <111>;
			regulator-name = "mgtravcc";
			regulator-min-microvolt = <850000>;
			regulator-max-microvolt = <850000>;
		};	
/* IRPS5401B
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/		
		uswap_val9k_mgtavcc_vu1: regulator@112 {
			compatible = "regulator-fixed";
			reg = <112>;
			regulator-name = "mgtavcc-vu1";
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <900000>;
		};
		
		uswap_val9k_mgtavcc_vu2: regulator@113 {
			compatible = "regulator-fixed";
			reg = <113>;
			regulator-name = "mgtavcc-vu2";
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <900000>;
		};	
			
		uswap_val9k_mgtavtt_vu1: regulator@114 {
			compatible = "regulator-fixed";
			reg = <114>;
			regulator-name = "mgtavtt-vu1";
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};		
	
		uswap_val9k_mgtavtt_vu2: regulator@115 {
			compatible = "regulator-fixed";
			reg = <115>;
			regulator-name = "mgtavtt-vu2";
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};
	
		uswap_val9k_mgtravtt: regulator@116 {
			compatible = "regulator-fixed";
			reg = <116>;
			regulator-name = "mgtravtt";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};		
	
/* LTM4678
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/		
		uswap_val9k_vccint_vu1: regulator@117 {
			compatible = "regulator-fixed";
			reg = <117>;
			regulator-name = "vccint-vu1";
			regulator-min-microvolt = <850000>;
			regulator-max-microvolt = <850000>;
		};	
	
/* LTM4678
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/		
		uswap_val9k_vccint_vu2: regulator@118 {
			compatible = "regulator-fixed";
			reg = <118>;
			regulator-name = "vccint-vu2";
			regulator-min-microvolt = <850000>;
			regulator-max-microvolt = <850000>;
		};		
	
	
/* LTM4676
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/		
		uswap_val9k_vccint_znq: regulator@119 {
			compatible = "regulator-fixed";
			reg = <119>;
			regulator-name = "vccint-znq";
			regulator-min-microvolt = <850000>;
			regulator-max-microvolt = <850000>;
		};	
		
		uswap_val9k_vccddr_1v2: regulator@120 {
			compatible = "regulator-fixed";
			reg = <120>;
			regulator-name = "vccddr-1v2";
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};
			
/* LTM4677
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/		
		uswap_val9k_vccintio: regulator@121 {
			compatible = "regulator-fixed";
			reg = <121>;
			regulator-name = "vccintio";
			regulator-min-microvolt = <850000>;
			regulator-max-microvolt = <850000>;
		};
10

Which again, leads me back to being able to pre-process the ‘top level DTS’ file

/*
 * Top level DTS file for CVM:P2888-0001 and CVB:P2822-0000.
 *
 * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */
#include "common/tegra194-p2888-0001-uswap_val9k-0000-common.dtsi"
#include "common/tegra194-p2822-camera-modules.dtsi"
#include "t19x-common-modules/tegra194-camera-plugin-manager.dtsi"

so I can spit out a new dtb from here, which should in theory, pull everything in…but that doesnt seem to be something anyone knows how to do…is that accurate?

11

For the dts file which gave errors during compile you might want to create a copy of it with a “.txt” file name suffix, and attach here. If you hover your mouse over the quote icon in the upper right of one of your existing posts, then a paper clip icon will also show up and you can attach with that.

I am uncertain how the “nvidia,dtsfilename” change would work. Typically the way I would approach is to flash and log the flash, then look at which dtb files were flashed. I’d then reverse compile those, and find which one contains the tree nodes which need adding or editing, and do basically the above procedure to those. Following that I’d flash (perhaps just flash the dtb).

Keep in mind as you go along that actual device tree flash procedures change depending on release, but if you’ve created a dtb, then you reverse compile again and verify the reverse compiled dts has the changes. Once those changes are in place, then you can boot the system and verify if the changes were dropped, and also know (due to reverse compiling your edited dtb) that the changes were present prior to the flash.

There are some edits made to the tree in the earlier boot stages prior to passing along to the Linux kernel, and perhaps you’ve run into that, but I don’t know.

12

Thanks for all your responses - nvidia should hire you if they aren’t already paying you. You seem to be the most knowledgeable person on the forums.

I will upload things Monday

13

Hi, Dan

I think you almost get there.

  1. dtsi is aim to share some models between different config file(You can treat the config file as the customized carry board) or differenct platform( like Tx2 or Xavier). It indeed works like some headers.
  2. dts is a devicetree set that can work as a standalone function like camera or the whole board. which don’t what to be shared and can be used as a target.
  3. I recommend to keep the directory structure pulled with the source_sync.sh script.
  4. Try to add the device tree file you want under the folder. hints: most device require to under its bus or host controller. So just follow the tree map and add the device node as a leaf. eg: i2c device should under its i2c bus. i2c@2560000 { mpu25@68 {} }
  5. ‘make dtbs’ under kernel directory will make all the targets board. make **.dtb will make the single **.dts.
  6. You can try to make a different target dtb files. copy and rename tegra186-quill-p3310-1000-a00-00-base.dts(for example) to a.dts and make a.dtb. recommend to reuse all the content in tegra186-quill-p3310-1000-a00-00-base.dts and modify the part acording to your device.
  7. Mostly one driver pairs with one devicetree node.
  8. When you compiled your devicetree, remember the timestamp and compile host. you can find it in the kernel boot log. If they are the same. The modification is sucessful.
  9. For Xavier the dtb file need to be encrypted by the flash tools and flashed to the corresponding partition to work otherwise the modification will take no effect. nothing will be changed.
  10. Recommend to use uart debug console to get more information. incase boot failed so that you can know where it fails.
  11. If you add mpu25@68 node to the devicetree and get the a.dtb after compiled, you can grep mpu25 a.dtb, mostly you can get it matched notice.
  12. DTS file is designed to make a clear tree for the hardware resource and easy to be reused by different board. It is widely used by the linux kernel. Split to different folder make the it more reuseable but indeed hard to find and understand.

Hope will help.

14

Hi,

I will try this when I get back to the Linux world.

I am back to other tasks for a few days.

-Dan

15

Hi,

I still think you guys are not understanding what I am trying to do.

I want to rebuild the DTB with the files i modified.

They are placed in the same folders as the originals…copies of them that I modified and renamed - as per the ‘best practice’ outlined in the adaptation guide.

What is missing is how to invoke the dtb to compile - honestly, it should be a series of CLI entries I would think.

I don’t understand why this is like pulling teeth…

Remember a time-stamp?

I want to build a modified DTB - your dev team built one using some combination of CLI entries and this pile of source files…why can’t we just be told what the steps were?

16

To be clear - I am not asking what a DTS, DTSI or DTB is.

I want to be able to say “nVidia make file, do your thing for DTB compilation, but start with MY top level .conf file and not yours”

17

So again, here is where I am at:

I have a new .conf and .conf.common file pair at the root folder of the P2888 L4T install on my host VM, not on the target - for me this location is:

/home/nvidia/nvidia_sdk/JetPack_4.2_Linux_P2888/Linux_for_Tegra

The file names are:
uswap_val9k-0000.conf
uswap_val9k-0000.conf.common

In the same way that the jetson-xavier.conf symbolic link references a .conf.common file for the p2792-0000, I have modified my .conf file to this:

#!/bin/bash

# Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#  * Redistributions of source code must retain the above copyright
#    notice, this list of conditions and the following disclaimer.
#  * Redistributions in binary form must reproduce the above copyright
#    notice, this list of conditions and the following disclaimer in the
#    documentation and/or other materials provided with the distribution.
#  * Neither the name of NVIDIA CORPORATION nor the names of its
#    contributors may be used to endorse or promote products derived
#    from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

# p2972-0000-devkit.conf: configuration for T194 Silicon

# Commenting this out and replacing with uswap_val9k file names
#source "${LDK_DIR}/p2972-0000.conf.common";
#PINMUX_CONFIG="tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg";
source "${LDK_DIR}/uswap_val9k-0000.conf.common";
PINMUX_CONFIG="tegra19x-uswap_val9k-gpiopinmux-1-1.cfg";

The other file referenced, my pinmux.cfg file was made using the workflow outlined in the nvidia documentation from the pin mux spreadsheet and it is sitting in the same folder as the other pinmux .cfg files - under Linux_for_Tegra/bootloader/t186ref/BCT

The .conf.common file reads:

# Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#  * Redistributions of source code must retain the above copyright
#    notice, this list of conditions and the following disclaimer.
#  * Redistributions in binary form must reproduce the above copyright
#    notice, this list of conditions and the following disclaimer in the
#    documentation and/or other materials provided with the distribution.
#  * Neither the name of NVIDIA CORPORATION nor the names of its
#    contributors may be used to endorse or promote products derived
#    from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

sub_var_token()
{
	local var="$1";
	local from="$2";
	local to="$3";
	if [ "${var}" != "" -a "${!var}" != "" ]; then
		if [[ "${!var}" =~ "${from}" ]]; then
			local val=`echo "${!var}" | sed -e s/${from}/${to}/`;
			eval "${var}=${val}";
		fi;
	fi;
}

process_board_version()
{
	local board_id="${1}";
	local board_version="${2}";
	local board_sku="${3}";
	local board_revision="${4}";
	local chiprev="${5}";
	local bdv=${board_version^^};
	local bid=${board_id^^};
	local fromfab="-a01";
	local frombpfab="${fromfab}.dtb";
	local tofab="-a01";		# default = A01
	local pmicfab="-a01";		# default = A01
	local bpfdtbfab="-a01.dtb";	# default = A01
	local tbcdtbfab="-a01";		# default = A01
	local kerndtbfab="-a01";	# default = A01
	local fromchip="a01-bpmp";	# default = A01
	local tochip="";

	# If no chip revision is passed default = A02
	# Only place this won't be passed as arg is --noflash option from
	# flash.sh where you can't probe the board.
	if [ "${chiprev}" = "0" ]; then
		chiprev="2";
		hwchiprev="${chiprev}";
	fi

	#
	# Board version is Alpha-Numeric value.
	#
	echo "Board ID(${board_id}) version(${board_version}) sku(${board_sku}) revision(${board_revision})" >/dev/stderr;
	if ! [[ "${bdv}" =~ ^[A-Z0-9][0-9][0-9]$ ]]; then
		bdv="${DEFAULT_FAB:-Z99}";
	fi;

	if [ "${bid}" \= "2888" ]; then
		if [ "${bdv}" \< "200" ]; then
			pmicfab="-a01";
		elif [ "${bdv}" \< "300" ]; then
			tofab="-a02";
			pmicfab="-a02";
			bpfdtbfab="-a02.dtb";
		elif [ "${bdv}" \< "500" ]; then
			tofab="-a02";
			pmicfab="-a04";
			bpfdtbfab="-a02.dtb";
			if [ \( "${board_sku}" \= "0004" \) -o \( "${bdv}" \> "300" -a "${board_revision}" \> "D.0" \) ]; then
				pmicfab="-a04-E-0";
				bpfdtbfab="-a04.dtb";
			fi;
		fi;
	elif [ "${bid}" \= "3360" ]; then
		if [ "${bdv}" \< "200" ]; then
			tofab="-a02";
			pmicfab="-a02";
		fi;
	fi

	#
	# BPFDTB_FILE	- chip, fab dependant
	# PINMUX_CONFIG	- no dependancy yet.
	# PMIC_CONFIG	- fab dependant
	# PMC_CONFIG	- no dependancy yet.
	# PROD_CONFIG	- no dependancy yet.
	# BOOTROM_CONFIG - no dependancy yet.
	# TBCDTB_FILE	- no dependancy yet.
	# DTB_FILE	- no dependancy yet.
	#
	sub_var_token "BPFDTB_FILE"    "${frombpfab}" "${bpfdtbfab}";
	sub_var_token "PINMUX_CONFIG"  "${fromfab}" "${tofab}";
	sub_var_token "PMIC_CONFIG"    "${fromfab}" "${pmicfab}";
	sub_var_token "PMC_CONFIG"     "${fromfab}" "${tofab}";
	sub_var_token "PROD_CONFIG"    "${fromfab}" "${tofab}";
	sub_var_token "BOOTROM_CONFIG" "${fromfab}" "${tofab}";
	sub_var_token "TBCDTB_FILE"    "${fromfab}" "${tbcdtbfab}";
	sub_var_token "DTB_FILE"       "${fromfab}" "${kerndtbfab}";

	if [ "${chiprev}" != "0" ]; then
		tochip="a0${chiprev}-bpmp";
		sub_var_token "BPFDTB_FILE"    "${fromchip}" "${tochip}";
	fi;
}

# Process fuse version:
#
# Non-fused BS vs Production Fused BD
#
# preboot_c10_dev_cr.bin vs. preboot_c10_prod_cr.bin
# mts_c10_dev_cr.bin     vs. mts_c10_prod_cr.bin
# mce_c10_dev_cr.bin     vs. mce_c10_prod_cr.bin
# mb1_t194_dev.bin       vs. mb1_t194_prod.bin
# warmboot_t194_dev.bin  vs. warmboot_t194_prod.bin
#
process_fuse_level()
{
	local fuselevel="${1}";
	local srctoken="_dev";
	local trgtoken="_prod";

	# fuselevel:
	#	"fuselevel_unknown"
	#	"fuselevel_nofuse"
	#	"fuselevel_production"
	#
	if [ "${fuselevel}" = "fuselevel_unknown" ]; then
		return;
	fi;
	if [ "${fuselevel}" = "fuselevel_nofuse" ]; then
		srctoken="_prod";
		trgtoken="_dev";
		sub_var_token "MTSPREBOOT" "preboot_c10_cr.bin" "preboot_c10_cr.bin";
		sub_var_token "MTS_MCE"    "mce_c10_cr.bin" "mce_c10_cr.bin";
		sub_var_token "MTSPROPER"  "mts_c10_cr.bin" "mts_c10_cr.bin";
	else
		sub_var_token "MTSPREBOOT" "preboot_c10_cr.bin" "preboot_c10_prod_cr.bin";
		sub_var_token "MTS_MCE"    "mce_c10_cr.bin" "mce_c10_prod_cr.bin";
		sub_var_token "MTSPROPER"  "mts_c10_cr.bin" "mts_c10_prod_cr.bin";
	fi;
	sub_var_token "MB1FILE"    "${srctoken}" "${trgtoken}";
	sub_var_token "SOSFILE"    "${srctoken}" "${trgtoken}";
	sub_var_token "WB0BOOT"    "${srctoken}" "${trgtoken}";
}

# Common values and/or defaults across p2972-0000*.conf:
# This section has been modified for uswap_val9k where appropriate

# ODMDATA is where UPHY lane mapping occurs - currently this value was set for the 2822 board
# Bits 31:27 control HSIO-PCIE-XBAR configurations for controllers 0-4, controller 
# Bits 24:23 control UFS configurations
# Bit 22 controls SATA 
#
#
# 2822 breakdown of settings
# 0x09190000 --> 0b00001 || 0b10 || 0b0 
# pcie-xbar-4-1-0-1-2 --> C0 = 4 lanes, C1 = 1 lanes, C2 = 0 lanes, C3 = 1 lanes, C4 = 2 lanes
# C0 = NVMe SSD (x4), C1 = eSATA (x1), C2 = Unused, C3 = M.2 Key E (x1), C4 = Unused (x2)
# UFS config = Enabled, L10 and L11
# This algins with the 2822 design, L10 is for the UFS card, and L11 is for eSATA
# SATA = disabled, this must be different from the eSATA controller.
#
#
# For val9k we want the following:
# 0x08190000 --> b00001 || 0b00 || 0b00
# C5 = x4 lanes (Zynq)
# pcie-xbar-4-1-0-1-2 
# C0 = NVMe SSD (x4), C1 = HBM1 (x1), C2 = Unused, C3 = HBM2 (x1), C4 = Unused (x2)
# UFS config = disabled
# SATA = disabled
#
#P2822 
#ODMDATA=0x09190000;
#
#uswap_val9k
ODMDATA=0x08190000;
CHIPID=0x19;
EMMC_CFG=flash_t194_sdmmc.xml;
BOOTPARTSIZE=8388608;
EMMCSIZE=31276924928;
ITS_FILE=;
# Seems pretty generic, not going to modify
SYSBOOTFILE=p2972-0000/extlinux.conf;
# This is the BPMP DTB file (boot and power management processor), probably don't need to 
# modify this since it is the SOM and not carrier. Made a copy and re-named for best practice
#
#P2822
#BPFDTB_FILE=tegra194-a01-bpmp-p2888-a01.dtb;
#
#uswap_val9k
BPFDTB_FILE=tegra194-a02-bpmp-p2888-a04-uswap_val9k.dtb;
#P2822 
#DTB_FILE=tegra194-p2888-0001-p2822-0000.dtb;
#
#uswap_val9k
DTB_FILE=tegra194-p2888-0001-uswap_val9k-0000.dtb;
#P2822
#TBCDTB_FILE=tegra194-p2888-0001-p2822-0000.dtb;
#
#uswap_val9k
TBCDTB_FILE=tegra194-p2888-0001-uswap_val9k-0000.dtb
ROOTFSSIZE=28GiB;
# This may need to be changed to be UART3?
CMDLINE_ADD="console=ttyTCU0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 rootfstype=ext4";
target_board="t186ref";
ROOT_DEV="mmcblk0p12 ------------ internal eMMC.
        sda1 ----------------- external USB devices. (USB memory stick, HDD)
        eth0 ----------------- nfsroot via RJ45 Ethernet port.
        eth1 ----------------- nfsroot via USB Ethernet interface.";
TEGRABOOT="bootloader/nvtboot_t194.bin";
WB0BOOT="bootloader/warmboot_t194_dev.bin";
FLASHAPP="bootloader/tegraflash.py";
FLASHER="bootloader/nvtboot_recovery_cpu_t194.bin";
BOOTLOADER="bootloader/nvtboot_cpu_t194.bin";
INITRD="bootloader/l4t_initrd.img";
TBCFILE="bootloader/cboot_t194.bin";
BPFFILE="bootloader/bpmp_t194.bin";
TOSFILE="bootloader/tos_t194.img";
EKSFILE="bootloader/eks.img";
MTSPREBOOT="bootloader/preboot_c10_cr.bin";
MTS_MCE="bootloader/mce_c10_cr.bin";
MTSPROPER="bootloader/mts_c10_cr.bin";
MB1FILE="bootloader/mb1_t194_dev.bin";
SOSFILE="bootloader/mb1_t194_dev.bin";
MB2BLFILE="bootloader/nvtboot_recovery_t194.bin";
SPEFILE="bootloader/spe_t194.bin";
CAMERAFW="bootloader/camera-rtcpu-rce.img";
MB2APPLET="nvtboot_applet_t194.bin"
FBFILE="fuse_bypass_t194.xml";
CBOOTOPTION_FILE="bootloader/cbo.dtb";

# BCT args:
#
BCT="--sdram_config";
BINSARGS="--bin \"";
# Unchanged
EMMC_BCT1="tegra194-memcfg-sw-override.cfg";
# Unchanged
EMMC_BCT="tegra194-mb1-bct-memcfg-p2888.cfg";
# Unchanged
MISC_CONFIG="tegra194-mb1-bct-misc-flash.cfg";
# Unchanged
MISC_COLD_BOOT_CONFIG="tegra194-mb1-bct-misc-l4t.cfg";
# Unchanged
BOOTROM_CONFIG="tegra194-mb1-bct-reset-p2888-0000-p2822-0000.cfg";
# Unchanged
DEV_PARAMS="tegra194-br-bct-sdmmc.cfg";
# Unchanged
SCR_COLD_BOOT_CONFIG="tegra194-mb1-bct-scr-cbb-mini.cfg";
# Unchanged
SCR_CONFIG="tegra194-mb1-bct-scr-cbb-mini.cfg";
# Modified for uswap_val9k from Excel pin mux table
PINMUX_CONFIG="tegra19x-uswap_val9k-gpiopinmux-1-1.cfg";
# Unchanged
PMIC_CONFIG="tegra194-mb1-bct-pmic-p2888-0001-a01-p2822-0000.cfg";
# Modified for uswap_val9k from Excel pin mux table
PMC_CONFIG="tegra19x-mb1-pad-uswap_val9k-1-1.cfg";
# Unchanged
PROD_CONFIG="tegra19x-mb1-prod-p2888-0000-p2822-0000.cfg";
# Unchanged
BR_CMD_CONFIG="tegra194-mb1-bct-reset-p2888-0000-p2822-0000.cfg";
# Unchanged
DEVICE_CONFIG="tegra19x-mb1-bct-device-sdmmc.cfg";
# Modified for uswap_val9k, removed lane 10 assignment from file
UPHY_CONFIG="tegra194-mb1-uphy-lane-p2888-0000-uswap_val9k-0000.cfg";
# Unchanged
GPIOINT_CONFIG="tegra194-mb1-bct-gpioint-p2888-0000-p2822-0000.cfg";
# Unchanged
SOFT_FUSES="tegra194-mb1-soft-fuses-l4t.cfg";
# Unchagned
NVKEY_FILE="t194_rsa_dev.key";
# Unchanged
NVENCRYPTKEY_FILE="t194_sbk_dev.key";

# Default FAB: Force Galen boards without properly programmed EEPROM.
# Values: A01 ->
#
DEFAULT_FAB="A01";

All modified .cfg files, which I have commented explicitly in this file, are in the same location as the files they replaced for the eval kit.

What I want to do, which seems like it should be so simple for you guys to answer - is to build a new kernel/DTB based off of this top level .conf/.conf.common file pair…

Can someone explain why this isn’t a ‘make’ at the CLI?

18

As per the design flow in nVidia documentation I also made modifications to some DTSI files, the power-tree DTSI files located at /sources/hardware/nvidia/platform/t19x/galen/kernel-dts/common - these are the files I renamed:

tegra194-power-tree-p2888-0001-p2822-1000.dtsi --> tegra194-power-tree-p2888-0001-uswap_val9k-0000.dtsi
tegra194-fixed-regulator-p2822-1000.dtsi --> tegra194-fixed-regulator-uswap_val9k-0000.dtsi

I also changed several ‘SoC Controller State’ DTSI files - these files are located at /sources/hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc:

tegra194-soc-i2c-uswap_val9k.dtsi
tegra194-soc-sdhci-uswap_val9k.dtsi
tegra194-soc-uart-uswap_val9k.dtsi

Here is the fixed-regulator file, which reflects our carrier design:

/*
 * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

/*
Files/entries that refer to 2888 are the SOM, any references to the 2822 from the original files may
* be modified or removed based on adaptation to the val9k PCB. This file is based on tegra194-fixed-regulator-uswap_val9k-1000.dtsi
* All entries here appear to be for the carrier board, so I am going to rename/replace with the regulators on the val9k board.
* Unsure what functionality this has in user space, but will be interested to see what happens at run time.
* We do not have any GPIO controlling supplies, so all of that will be removed, which probably makes the include for GPIO 
* useless...but i'll leave it there.
* I am going from page 1 to page 122 and adding entries here in that order. Based on rev 7 of the schematic. AST010-0035
* Local low current LDOs that are not included right now:
* VCC_12V, VCC_5V: VPX supplied voltages, main input power rails to the Xavier, but not defined here in reference file.
* VREF_2V5: For I2C Buffer, powered by VPX backplane
* VREF_1V8: For I2C Buffer and sequence GPIO, powered by VPX backplane
* VPX_3V3: For sequence/reset logic, powered by VPX backplane
* VCC_ADC_ZNQ: Reference voltage for Zynq MpSOC ADC
* VCC_ADC_VU1: Creates 1v25 reference voltage for HBM1 ADC
* VCC_ADC_VU2: Creates 1v25 reference voltage for HBM2 ADC
* VCC_XAVPHY_1V0, VCC_XAVPHY_1V8: Internally derived voltages for the ENET PHY attached to Xavier
* VCC_ZNQPHY_1V0, VCC_ZNQPHY_1V8: Internally derived voltages for the ENET PHY attached to Zynq
* VCC_UARTA_VBUS: 5V from USB UART port connected to Zynq. Does not power anything on the board, not under GPIO control
* VCC_UARTB_VBUS: 5V from USB UART port connected to Xavier. Does not power anything on the board, not under GPIO control
* Separate entries for devices like: QSPI flash, SD Cards, PCIe (NVMe) that are powered directly by other regualtors, and are not under GPIO control. 
* We may need to add 'regulator' entries to some Xavier connected peripherals to have a valid DTB. Also might be able to re-use the same entries as below for 3v3 etc.
 */

#include <dt-bindings/gpio/tegra194-gpio.h>

/ {
	fixed-regulators {
/* LTM4686
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/	
		uswap_val9k_vcc_3v3_main: regulator@101 {
			compatible = "regulator-fixed";
			reg = <101>;
			regulator-name = "vcc-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};

		uswap_val9k_vaux_1v8: regulator@102 {
			compatible = "regulator-fixed";
			reg = <102>;
			regulator-name = "vaux-1v8";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};
/* TPS51200*/
		uswap_val9k_ddr4_vtt: regulator@104 {
			compatible = "regulator-fixed";
			reg = <104>;
			regulator-name = "ddr4-vtt";
			regulator-min-microvolt = <600000>;
			regulator-max-microvolt = <600000>;
		};

/* This is a load switch output, but is not under control of the xavier, discrete logic controls the supply rails*/		
		uswap_val9k_vccfmc_12v: regulator@105 {
			compatible = "regulator-fixed";
			reg = <105>;
			regulator-name = "vccfmc-12v";
			regulator-min-microvolt = <12000000>;
			regulator-max-microvolt = <12000000>;
		};
/* This is a load switch output, but is not under control of the xavier, discrete logic controls the supply rails*/		
		uswap_val9k_vccfmc_adj: regulator@106 {
			compatible = "regulator-fixed";
			reg = <106>;
			regulator-name = "vccfmc-adj";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};	
/* IRPS5401A
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/	
		uswap_val9k_mgtavcc_znq: regulator@107 {
			compatible = "regulator-fixed";
			reg = <107>;
			regulator-name = "mgtavcc-znq";
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <900000>;
		};
		
		uswap_val9k_vccaux_2v5: regulator@108 {
			compatible = "regulator-fixed";
			reg = <108>;
			regulator-name = "vccaux-2v5";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
		};	
			
		uswap_val9k_mgtavtt_znq: regulator@109 {
			compatible = "regulator-fixed";
			reg = <109>;
			regulator-name = "mgtavtt-znq";
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};		
	
		uswap_val9k_vccint_vcu: regulator@110 {
			compatible = "regulator-fixed";
			reg = <110>;
			regulator-name = "vccint-vcu";
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <900000>;
		};
		
		uswap_val9k_mgtravcc: regulator@111 {
			compatible = "regulator-fixed";
			reg = <111>;
			regulator-name = "mgtravcc";
			regulator-min-microvolt = <850000>;
			regulator-max-microvolt = <850000>;
		};	
/* IRPS5401B
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/		
		uswap_val9k_mgtavcc_vu1: regulator@112 {
			compatible = "regulator-fixed";
			reg = <112>;
			regulator-name = "mgtavcc-vu1";
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <900000>;
		};
		
		uswap_val9k_mgtavcc_vu2: regulator@113 {
			compatible = "regulator-fixed";
			reg = <113>;
			regulator-name = "mgtavcc-vu2";
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <900000>;
		};	
			
		uswap_val9k_mgtavtt_vu1: regulator@114 {
			compatible = "regulator-fixed";
			reg = <114>;
			regulator-name = "mgtavtt-vu1";
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};		
	
		uswap_val9k_mgtavtt_vu2: regulator@115 {
			compatible = "regulator-fixed";
			reg = <115>;
			regulator-name = "mgtavtt-vu2";
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};
	
		uswap_val9k_mgtravtt: regulator@116 {
			compatible = "regulator-fixed";
			reg = <116>;
			regulator-name = "mgtravtt";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};		
	
/* LTM4678
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/		
		uswap_val9k_vccint_vu1: regulator@117 {
			compatible = "regulator-fixed";
			reg = <117>;
			regulator-name = "vccint-vu1";
			regulator-min-microvolt = <850000>;
			regulator-max-microvolt = <850000>;
		};	
	
/* LTM4678
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/		
		uswap_val9k_vccint_vu2: regulator@118 {
			compatible = "regulator-fixed";
			reg = <118>;
			regulator-name = "vccint-vu2";
			regulator-min-microvolt = <850000>;
			regulator-max-microvolt = <850000>;
		};		
	
	
/* LTM4676
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/		
		uswap_val9k_vccint_znq: regulator@119 {
			compatible = "regulator-fixed";
			reg = <119>;
			regulator-name = "vccint-znq";
			regulator-min-microvolt = <850000>;
			regulator-max-microvolt = <850000>;
		};	
		
		uswap_val9k_vccddr_1v2: regulator@120 {
			compatible = "regulator-fixed";
			reg = <120>;
			regulator-name = "vccddr-1v2";
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};
			
/* LTM4677
 * This one is adjustable, via PMBUS. When we do that (if we do that) this probably changes the entry type*/		
		uswap_val9k_vccintio: regulator@121 {
			compatible = "regulator-fixed";
			reg = <121>;
			regulator-name = "vccintio";
			regulator-min-microvolt = <850000>;
			regulator-max-microvolt = <850000>;
		};						

		
/* This entry was renamed based on the power tree change, and the GPIO and enable were removed based on the val9k design*/
/* Commented out because on val9k we do not have load switch for SDMMC
		uswap_valk9k_vdd_sdmmc1: regulator@122 {
			compatible = "regulator-fixed";
			reg = <122>;
			regulator-name = "vdd-sdmmc1";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};*/

	};
};

In this same folder location (/sources/hardware/nvidia/platform/t19x/galen/kernel-dts/common) I have made copies of all the files that I needed to modify and appended the names with our project name. I then went into those files and modified #include statements to point to the new files:

e.g.) tegra194-p2888-0001-uswap_val9k-0000-common.dtsi

/*
 * Common include DTS file for uswap_val9k alion design.
 *
 * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

/*Not a real file?*/
/*#include "dt-bindings/extcon-ids.h"*/
/*Unchanged*/
#include "dt-bindings/gpio/tegra194-gpio.h"
/*This needs to be changed to pull in the i2c, sdhci, uart and pcie changes made*/
#include "tegra194-p2888-0000-a00-uswap_val9k.dtsi"
/*Unchanged*/
#include <t19x-common-platforms/tegra194-platforms-eqos.dtsi>
/*Unchanged, only oddity here may be the 'power key' entry*/
#include "tegra194-p2822-0000-a00.dtsi"
/*Changed to uswap_val9k*/
#include "tegra194-power-tree-p2888-0001-uswap_val9k-0000.dtsi"\
/*Unchanged*/
#include <t19x-common-platforms/tegra194-comms.dtsi>
/*Unchanged*/
#include "tegra194-thermal-p2888.dtsi"
/*Unchanged*/
#include "tegra194-plugin-manager-p2888-0000.dtsi"
/*Unchanged*/
#include "tegra194-plugin-manager-p2822-0000.dtsi"
/*Unchanged*/
#include "tegra194-super-module-e2614-p2888-0000.dtsi"

/ {
	nvidia,dtsfilename = __FILE__;
	nvidia,dtbbuildtime = __DATE__, __TIME__;
	nvidia,fastboot-usb-vid = <0x0955>;
	nvidia,fastboot-usb-pid = <0xee1e>;
	model = "jetson-xavier";

	compatible = "nvidia,jetson-xavier", "nvidia,tegra194";

	chosen {
		bootargs ="console=ttyTCU0,115200";
		board-has-eeprom;
	};

	firmware {
		android {
			compatible = "android,firmware";
			hardware = "jetson-xavier";
			vbmeta {
				compatible = "android,vbmeta";
				parts = "vbmeta,kernel,kernel-dtb,APP,vendor,SOS";
			};
			fstab {
				compatible = "android,fstab";
				vendor {
					compatible = "android,vendor";
					dev = "/dev/block/platform/3460000.sdhci/by-name/vendor";
					type = "ext4";
					mnt_flags = "ro";
					fsmgr_flags = "wait,avb";
				};
				odm {
					compatible = "android,odm";
					dev = "/dev/block/platform/3460000.sdhci/by-name/odm";
					type = "ext4";
					mnt_flags = "ro";
					fsmgr_flags = "wait,avb";
				};
			};
		};
	};

	spi@c260000 {
		status = "disabled";
	};

	spi@3270000 {
		status = "disabled";
	};

	spi@3300000 {
		status = "disabled";
	};

	pmc@c370000 {
		nvidia,invert-interrupt;
	};

	i2c@c240000 {
		bmi160@69 {
			compatible = "bmi,bmi160";
			reg = <0x69>;
			interrupt-parent = <&tegra_aon_gpio>;
			interrupts = <TEGRA194_AON_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
			accelerometer_matrix    = [01 00 00 00 01 00 00 00 01];
			gyroscope_matrix        = [01 00 00 00 01 00 00 00 01];
			accelerometer_delay_us_min = <1250>;
			gyroscope_delay_us_min = <1250>;
			status = "okay";
		};
		ucsi_ccg: ucsi_ccg@8 {
			status = "okay";
			typec-extcon {
				typec_port0: port-0 {
					status = "okay";
					#extcon-cells = <1>;
				};
				typec_port1: port-1 {
					status = "okay";
					#extcon-cells = <1>;
				};
			};
			typec-pd {
				typec_pd: pd {
					status = "okay";
					#extcon-cells = <1>;
				};
			};
		};
	};

#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2

	xusb_padctl: xusb_padctl@3520000 {
		status = "okay";

		pads {
			usb2 {
				lanes {
					usb2-0 {
						nvidia,function = "xusb";
						status = "okay";
					};
					usb2-1 {
						nvidia,function = "xusb";
						status = "okay";
					};
					usb2-2 {
						nvidia,function = "xusb";
						status = "okay";
					};
					usb2-3 {
						nvidia,function = "xusb";
						status = "okay";
					};
				};
			};
			usb3 {
				lanes {
					usb3-0 {
						nvidia,function = "xusb";
						status = "okay";
					};
					usb3-2 {
						nvidia,function = "xusb";
						status = "okay";
					};
					usb3-3 {
						nvidia,function = "xusb";
						status = "okay";
					};
				};
			};
		};

		ports {
			usb2-0 {
				mode = "otg";
				status = "okay";
			};
			usb2-1 {
				mode = "host";
				status = "okay";
			};
			usb2-2 {
				mode = "host";
				status = "okay";
			};
			usb2-3 {
				mode = "host";
				status = "okay";
			};
			usb3-0 {
				nvidia,usb2-companion = <1>;
				status = "okay";
			};
			usb3-2 {
				nvidia,usb2-companion = <0>;
				status = "okay";
			};
			usb3-3 {
				nvidia,usb2-companion = <3>;
				nvidia,usb3-gen1-only= <1>;
				status = "okay";
			};
		};
	};
#endif

	tegra_xudc: xudc@3550000 {
		extcon-cables = <&typec_port0 0>;
		extcon-cable-names = "vbus";
		#extcon-cells = <1>;
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
		phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>,
			<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-2}>;
		phy-names = "usb2", "usb3";
		nvidia,xusb-padctl = <&xusb_padctl>;
#endif
		nvidia,boost_cpu_freq = <1200>;
		status = "okay";
	};

	tegra_xhci: xhci@3610000 {
		extcon-cables = <&typec_port0 1>;
		extcon-cable-names = "id";
		#extcon-cells = <1>;
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
		phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>,
			<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-1}>,
			<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-3}>,
			<&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-2}>,
			<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-2}>,
			<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-0}>,
			<&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-3}>;
		phy-names = "usb2-0", "usb2-1", "usb2-3", "usb2-2",
			"usb3-2", "usb3-0", "usb3-3";
		nvidia,xusb-padctl = <&xusb_padctl>;
#endif
		status = "okay";
	};

	arm-pmu {
		status = "okay";
	};

	power-domain {
		status = "disabled";
	};

	interrupt-controller {
		status = "disabled";
	};

	mods-simple-bus {
		status = "disabled";
	};

	eeprom-manager {
		status = "disabled";
	};

	cpuidle {
		compatible = "nvidia,tegra19x-cpuidle";
		status = "okay";
	};

	thermal-zones {
		status = "disabled";
	};

	reserved-memory {
		ramoops_carveout {
			status = "okay";
		};
	};

	mttcan@c310000 {
		status = "okay";
	};

	mttcan@c320000 {
		status = "okay";
	};

	serial@3110000 {
		status = "okay";
	};

	pwm@32c0000 {
		status = "okay";
	};

	pwm@32f0000 {
		status = "okay";
	};

	i2c@31e0000 {
		pinctrl-names = "default";
		pinctrl-0 = <&dpaux_default>;
		bmi160@69 {
			compatible = "bmi,bmi160";
			reg = <0x69>;
			accelerometer_matrix    = [01 00 00 00 01 00 00 00 01];
			gyroscope_matrix        = [01 00 00 00 01 00 00 00 01];
			status = "okay";
		};
	};

	host1x {
		dpaux@155F0000 {
			status = "okay";
			compatible = "nvidia,tegra194-dpaux3-padctl";
			/delete-property/ power-domains;
			dpaux_default: pinmux@0 {
				dpaux3_pins {
					pins = "dpaux3-3";
					function = "i2c";
				};
			};
		};
	};

	hardwood {
		compatible = "nvidia,denver-hardwood";
		interrupts = <0 24 0x4>;
	};

	ufshci@2450000 {
		nvidia,enable-hs-mode;
	};
};

&head0 {
	extcon-cables = <&typec_port0 2 &typec_port1 2>;
	extcon-cable-names = "typec0", "typec1";
	#extcon-cells = <1>;
};

&head1 {
	extcon-cables = <&typec_port0 2 &typec_port1 2>;
	extcon-cable-names = "typec0", "typec1";
	#extcon-cells = <1>;
};

&head2 {
	extcon-cables = <&typec_port0 2 &typec_port1 2>;
	extcon-cable-names = "typec0", "typec1";
	#extcon-cells = <1>;
};

&sor0 {
	nvidia,typec-port = /bits/ 8 <0>;
};

&sor1 {
	nvidia,typec-port = /bits/ 8 <1>;
};

#if LINUX_VERSION >= 414
#include <tegra194-linux-4.14.dtsi>
#endif

So based on the workflow outlined in nVidia’s documentation, I did all of this work. I would like to understand how to pull it all together. Since these files use a cpp pre-processor (#includes used) you need to invoke runtime environment variables etc to point to toolchains etc.

Can someone provide some assistance?

My company has an NDA with nVidia - it should be WAY easier to get help with this, it’s not as though I’m asking them to do all the work…

19

If you are compiling natively, and if the kernel source is configured to match your existing system, then the simplest command in the kernel source is:

make dtbs

Out of tree options for native compile might be something like:

export TEGRA_KERNEL_OUT=/some/where/convenient
make O=$TEGRA_KERNEL_OUT dtbs

The key is that you are building a kernel and the target is “dtbs”.

20

I think I did that but it didnt make the new one…