CSI_A syncpt timeout issue

Hi,

We try to chain image sensor OV10633 via Toshiba parallel to MIPI bridge TC358746XBG then input 720p YUV422 8bit 30fps 4lanes data to TK1.

We have hooked an OV10633 camera module to a Jetson Tk1 devkit. The camera module was detected and i2c path works properly and after loading the camera host driver (tegra_camera) we had a v4l device.

Further settings are done via user space(Toshiba TC358746XBG initial, etc.) So we used V4L2 API for setting up de OV10633 module and TC358746XBG through i2c. After doing so, we see communication on the MIPI bus. When we try to access the v4l device, the linux reply debug message as follow,

[ 339.153039] ov10633_s_stream --> ov10633_write_table!
[ 339.358271] vi vi.0: CSI_A syncpt timeout, syncpt = 6, err = -11
[ 339.365539] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 339.374458] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 339.379993] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 339.385223] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 339.390940] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 339.396071] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 339.401237] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 339.407051] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 339.412953] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 339.418018] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 339.623110] vi vi.0: CSI_A syncpt timeout, syncpt = 7, err = -11
[ 339.630189] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 339.636191] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 339.641775] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 339.647202] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 339.652700] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 339.657648] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 339.662521] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 339.668473] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 339.674233] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 339.679324] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 339.884269] vi vi.0: CSI_A syncpt timeout, syncpt = 8, err = -11
[ 339.892978] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 339.905089] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 339.909986] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 339.915230] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 339.920154] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 339.925071] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 339.929990] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 339.935677] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 339.941336] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 339.946514] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 340.150747] vi vi.0: CSI_A syncpt timeout, syncpt = 9, err = -11
[ 340.158091] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 340.166325] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 340.173220] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 340.178169] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 340.183517] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 340.188456] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 340.193705] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 340.199364] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 340.205196] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 340.210174] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 340.414544] vi vi.0: CSI_A syncpt timeout, syncpt = 10, err = -11
[ 340.421846] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 340.427214] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 340.432831] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 340.439079] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 340.448793] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 340.453861] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 340.459006] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 340.464682] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 340.470540] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 340.475926] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 340.680387] vi vi.0: CSI_A syncpt timeout, syncpt = 11, err = -11
[ 340.688649] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 340.698815] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 340.703922] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 340.709593] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 340.714636] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 340.719542] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 340.724689] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 340.730412] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 340.736308] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 340.741255] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 340.945280] vi vi.0: CSI_A syncpt timeout, syncpt = 12, err = -11
[ 340.957978] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 340.966734] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 340.973500] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 340.979856] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 340.986948] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 340.992032] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 340.997083] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 341.003204] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 341.008834] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 341.013995] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 341.219071] vi vi.0: CSI_A syncpt timeout, syncpt = 13, err = -11
[ 341.236002] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 341.243104] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 341.249034] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 341.253989] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 341.258989] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 341.264020] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 341.268998] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 341.274628] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 341.280364] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 341.285584] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
select timeout
[ 341.490095] vi vi.0: CSI_A syncpt timeout, syncpt = 14, err = -11
[ 341.499697] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 341.511183] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 341.516150] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 341.521200] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 341.526082] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 341.531417] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 341.536334] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 341.542152] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 341.547806] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 341.552910] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 341.757583] vi vi.0: CSI_A syncpt timeout, syncpt = 15, err = -11
[ 341.764596] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 341.770767] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 341.780084] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 341.785475] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 341.790945] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 341.796159] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 341.801196] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 341.806871] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 341.812884] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 341.818004] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 342.032510] vi vi.0: CSI_A syncpt timeout, syncpt = 16, err = -11
[ 342.040501] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 342.048924] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 342.059977] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 342.065611] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 342.070519] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 342.075484] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 342.080416] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 342.086259] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 342.092217] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 342.097209] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000

Please help to confirm the debug message. We used oscilloscope to check MIPI CSI_A_CLK(120MHz), CSI_A_D0/1, CSI_B_D0/1 signal is working but TK1 CSI_A syncpt timeout.

If available, please support any suggestion or direction to overcome this issue. Any help will be sincerely appreciated. Thanks.

Hi,

Could you please give me a few pointers with CSI_A syncpt timeout issue? I would appreciate it if you could take a moment to explain something to me. Thanks.

From the message you post, there seems some ctrl error from clk lane, which means CSI phy detects incorrect line state sequence on clk lane.

[ 342.048924] TEGRA_CSI_CSI_CILA_STATUS 0x00000001

Which clk mode are you using? discontinuous or continuous? Please ensure it’s configured appropriately along with the sensor output.

Hi, nVConan,

Thanks for your reply.

In the arch/mach-tegra/arm/board-ardbeg-sensors.c, we follow imx135 setting to set ov10633 tegra_camera_platform_data .continuous_clk = 0, because ov10633 and TC358746XBG clock source come from TK1. Would we need to change it?

By the way, according to https://devtalk.nvidia.com/default/topic/932750/ov5693_v4l2-changing-from-csi_c-to-csi_a-/
Would we need to add entries in dtsi file for ov10633 and also in board file? CSI syncpoint error because haven’t done any entry in dtsi file? But our ov10633 does not use any regulator.

Thanks for your help.

The clk mode depends on the real output of ov10633 and toshiba bridge (note clk lanes are not generated from Tegra), if you are not sure about the clk mode, you can contact FAE. Generally, the clk mode can be changed from sensor/bridge i2c register table.
You don’t need to add any dtsi file, since the topic you mentioned is for TX1 and L4T R23.2 release, so it can’t be applied here.

Probably you can contact toshiba regarding the mipi clk mode of bridge output.

Hi, nVConan,

Thanks for your direction.

Here is other debug message,
[ 86.834399] ov10633_s_stream --> ov10633_write_table!
[ 87.040676] vi vi.0: CSI_A syncpt timeout, syncpt = 1, err = -11
[ 87.048435] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 87.054347] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 87.059956] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 87.065695] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 87.071958] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 87.077876] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 87.083615] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 87.089491] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 87.095651] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 87.101185] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 87.306919] vi vi.0: CSI_A syncpt timeout, syncpt = 2, err = -11
[ 87.322920] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 87.332042] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 87.336997] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 87.342307] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 87.347263] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 87.352251] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 87.357614] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 87.363876] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 87.369875] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 87.375029] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 87.580662] vi vi.0: CSI_A syncpt timeout, syncpt = 3, err = -11
[ 87.589579] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 87.594516] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 87.599364] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 87.604292] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 87.611581] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 87.616580] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 87.621576] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 87.627233] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 87.634608] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 87.640093] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 87.844617] vi vi.0: CSI_A syncpt timeout, syncpt = 4, err = -11
[ 87.852686] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 87.857547] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 87.862332] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 87.867528] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 87.872691] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 87.877786] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 87.884601] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 87.890333] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 87.895989] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 87.902599] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 88.106695] vi vi.0: CSI_A syncpt timeout, syncpt = 5, err = -11
[ 88.115616] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 88.120634] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 88.125449] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 88.130399] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 88.137593] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 88.142687] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 88.147792] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 88.153406] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 88.160592] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 88.166337] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 88.371069] vi vi.0: CSI_A syncpt timeout, syncpt = 6, err = -11
[ 88.379478] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 88.384419] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 88.389231] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 88.394274] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 88.399319] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 88.404580] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 88.409613] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 88.415489] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 88.421237] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 88.426575] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 88.630739] vi vi.0: CSI_A syncpt timeout, syncpt = 7, err = -11
[ 88.638666] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 88.644765] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 88.650659] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 88.656215] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 88.663786] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 88.668637] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 88.674075] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 88.680232] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 88.686286] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 88.691581] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 88.896684] vi vi.0: CSI_A syncpt timeout, syncpt = 8, err = -11
[ 88.904605] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 88.910008] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 88.914848] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 88.919663] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 88.924460] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 88.929630] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 88.934438] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 88.940116] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 88.945744] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 88.951187] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
select timeout
[ 89.156709] vi vi.0: CSI_A syncpt timeout, syncpt = 9, err = -11
[ 89.164615] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 89.169511] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 89.174308] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 89.179191] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 89.184085] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 89.189148] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 89.194128] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 89.199796] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 89.205343] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 89.210379] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 89.415695] vi vi.0: CSI_A syncpt timeout, syncpt = 10, err = -11
[ 89.423655] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 89.428700] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 89.433477] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 89.438265] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 89.443036] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 89.448166] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 89.452940] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 89.458521] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 89.464066] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 89.469593] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 89.681605] vi vi.0: CSI_A syncpt timeout, syncpt = 11, err = -11
[ 89.688591] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 89.693429] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 89.698338] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 89.703134] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 89.707909] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 89.712787] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 89.717594] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 89.723164] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 89.728731] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 89.733697] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 89.939610] vi vi.0: CSI_A syncpt timeout, syncpt = 12, err = -11
[ 89.946595] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 89.951389] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 89.956124] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 89.960888] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 89.965695] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 89.970634] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 89.975438] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 89.981339] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 89.987599] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 89.992695] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 90.196612] vi vi.0: CSI_A syncpt timeout, syncpt = 13, err = -11
[ 90.203597] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 90.208390] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 90.213158] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 90.217944] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 90.222803] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 90.227672] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 90.232472] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 90.238042] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 90.243587] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 90.248546] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 90.453618] vi vi.0: CSI_A syncpt timeout, syncpt = 14, err = -11
[ 90.460618] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 90.465634] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 90.470362] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 90.475122] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 90.479932] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 90.484791] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 90.489549] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 90.495118] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 90.500690] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 90.506601] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 90.710620] vi vi.0: CSI_A syncpt timeout, syncpt = 15, err = -11
[ 90.717603] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 90.722390] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 90.727212] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 90.731978] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 90.736738] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 90.741602] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 90.746399] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 90.752028] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 90.757568] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 90.763616] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 90.967619] vi vi.0: CSI_A syncpt timeout, syncpt = 16, err = -11
[ 90.974605] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 90.979389] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 90.984063] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 90.988856] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 90.993722] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 90.998484] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 91.003345] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 91.009605] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 91.015250] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 91.020099] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 91.224637] vi vi.0: CSI_A syncpt timeout, syncpt = 17, err = -11
[ 91.231136] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 91.236296] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 91.241293] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 91.246444] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 91.251512] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 91.256550] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 91.261607] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 91.267392] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 91.272986] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 91.278219] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 91.482629] vi vi.0: CSI_A syncpt timeout, syncpt = 18, err = -11
[ 91.489614] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 91.494424] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 91.499220] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 91.504005] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 91.508837] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 91.513755] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 91.518537] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 91.524203] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 91.530608] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 91.535589] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 91.739635] vi vi.0: CSI_A syncpt timeout, syncpt = 19, err = -11
[ 91.746617] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 91.751499] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 91.756425] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 91.761226] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 91.766026] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 91.771066] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 91.776016] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 91.781694] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 91.787275] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 91.793615] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 91.997646] vi vi.0: CSI_A syncpt timeout, syncpt = 20, err = -11
[ 92.005619] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 92.010485] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 92.015535] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 92.020455] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 92.025296] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 92.030386] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 92.035269] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 92.040995] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 92.046599] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 92.051718] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 92.263634] vi vi.0: CSI_A syncpt timeout, syncpt = 21, err = -11
[ 92.270000] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000010
[ 92.289044] TEGRA_CSI_CSI_CILA_STATUS 0x00040041
[ 92.303464] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000010
[ 92.308423] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 92.315267] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 92.320184] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 92.327455] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 92.335954] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 92.341787] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 92.346877] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 92.558635] vi vi.0: CSI_A syncpt timeout, syncpt = 22, err = -11
[ 92.568623] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000010
[ 92.574625] TEGRA_CSI_CSI_CILA_STATUS 0x00040041
[ 92.584624] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000010
[ 92.594626] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 92.603624] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 92.613626] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 92.620656] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 92.631649] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 92.643626] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 92.652624] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 92.862918] vi vi.0: CSI_A syncpt timeout, syncpt = 23, err = -11
[ 92.872166] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000010
[ 92.877968] TEGRA_CSI_CSI_CILA_STATUS 0x00040041
[ 92.882808] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000010
[ 92.887659] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 92.893098] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 92.897971] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 92.902781] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 92.908420] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 92.914068] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 92.919188] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000

We are not sure why TEGRA_CSI_CSI_CILA_STATUS from 0x00000001 to 0x00040041? And V4L2 response select timeout. We will confirm clock mode with OV and Toshiba local agent. We are struggling to overcome this issue a couple of weeks.

Hi, nVConan,

The Toshiba local agent release 4-lanes, non-continuous clock mode register table for us. We try it and the debug message as follow,
[ 98.346747] ov10633_s_stream --> ov10633_write_table!
[ 98.552114] vi vi.0: CSI_A syncpt timeout, syncpt = 1, err = -11
[ 98.560348] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 98.566964] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 98.572882] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 98.578652] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 98.584161] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 98.589208] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 98.594715] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 98.600532] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 98.606575] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 98.611812] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 98.816880] vi vi.0: CSI_A syncpt timeout, syncpt = 2, err = -11
[ 98.834189] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 98.847825] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 98.853219] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 98.858420] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 98.863362] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 98.868661] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 98.875832] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 98.881594] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 98.887364] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000008
[ 98.892498] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 99.097757] vi vi.0: CSI_A syncpt timeout, syncpt = 3, err = -11
[ 99.113749] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 99.132787] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 99.138208] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 99.143515] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 99.148498] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 99.154390] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 99.159946] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 99.165780] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 99.171615] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000008
[ 99.176870] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 99.383023] vi vi.0: CSI_A syncpt timeout, syncpt = 4, err = -11
[ 99.398413] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 99.407579] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 99.412384] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 99.417356] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 99.422308] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 99.427198] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 99.432042] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 99.438095] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 99.443757] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000008
[ 99.448906] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 99.654247] vi vi.0: CSI_A syncpt timeout, syncpt = 5, err = -11
[ 99.672138] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 99.686955] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 99.691973] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 99.696851] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 99.701892] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 99.706789] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 99.711909] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 99.717645] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 99.723374] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000008
[ 99.728606] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 99.934339] vi vi.0: CSI_A syncpt timeout, syncpt = 6, err = -11
[ 99.949945] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 99.961136] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 99.970520] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 99.976026] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 99.981084] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 99.986054] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 99.991093] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 99.996954] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 100.002705] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000008
[ 100.007861] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 100.212328] vi vi.0: CSI_A syncpt timeout, syncpt = 7, err = -11
[ 100.219419] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 100.224909] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 100.230104] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 100.235138] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 100.240800] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 100.246511] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 100.251484] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 100.257267] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 100.263163] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000008
[ 100.268166] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 100.480051] vi vi.0: CSI_A syncpt timeout, syncpt = 8, err = -11
[ 100.501265] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 100.507175] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 100.512154] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 100.517074] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 100.522561] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 100.527876] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 100.532976] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 100.538738] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 100.544509] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000008
[ 100.549451] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
select timeout
[ 100.754983] vi vi.0: CSI_A syncpt timeout, syncpt = 9, err = -11
[ 100.770887] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 100.784502] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 100.789861] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 100.795109] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 100.800073] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 100.805366] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 100.810838] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 100.816503] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 100.822208] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000008
[ 100.827335] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 101.032611] vi vi.0: CSI_A syncpt timeout, syncpt = 10, err = -11
[ 101.048697] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 101.062152] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 101.067738] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 101.073079] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 101.078030] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 101.083750] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 101.088859] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 101.095011] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 101.100763] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000008
[ 101.105982] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 101.317772] vi vi.0: CSI_A syncpt timeout, syncpt = 11, err = -11
[ 101.324944] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000010
[ 101.330042] TEGRA_CSI_CSI_CILA_STATUS 0x00040041
[ 101.336041] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000010
[ 101.340959] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 101.346018] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 101.350990] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 101.356256] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 101.362062] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 101.367730] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 101.373240] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 101.580137] vi vi.0: CSI_A syncpt timeout, syncpt = 12, err = -11
[ 101.599270] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000010
[ 101.604444] TEGRA_CSI_CSI_CILA_STATUS 0x00040041
[ 101.609861] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000010
[ 101.614902] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 101.620464] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 101.625344] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 101.630315] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 101.636033] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 101.641708] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 101.646991] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000

The TEGRA_CSI_CSI_CILA_STATUS from 0x00000001 to 0x00000000, but TEGRA_VI_CSI_0_ERROR_STATUS from 0x00000000 to 0x00000008. It look like TEGRA_CSI_CSI_CILA_STATUS improve but TEGRA_VI_CSI_0 get some error. Have I missed something?

Hi, nVConan,

After received 2 frames, the TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000080 and TEGRA_VI_CSI_0_ERROR_STATUS 0x0000000c. If available, please help to overcome this issues. Any help will be sincerely appreciated. Thanks.

[ 1770.005173] ov10633_s_stream --> ov10633_write_table!
size = 1843200
size = 1843200
[ 1770.424347] vi vi.0: CSI_A syncpt timeout, syncpt = 3, err = -11
[ 1770.443453] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 1770.454163] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 1770.459528] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 1770.464837] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 1770.469810] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 1770.474695] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 1770.479680] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000080
[ 1770.485527] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 1770.491170] TEGRA_VI_CSI_0_ERROR_STATUS 0x0000000c
[ 1770.496304] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000