Hi,
We try to chain image sensor OV10633 via Toshiba parallel to MIPI bridge TC358746XBG then input 720p YUV422 8bit 30fps 4lanes data to TK1.
We have hooked an OV10633 camera module to a Jetson Tk1 devkit. The camera module was detected and i2c path works properly and after loading the camera host driver (tegra_camera) we had a v4l device.
Further settings are done via user space(Toshiba TC358746XBG initial, etc.) So we used V4L2 API for setting up de OV10633 module and TC358746XBG through i2c. After doing so, we see communication on the MIPI bus. When we try to access the v4l device, the linux reply debug message as follow,
[ 339.153039] ov10633_s_stream → ov10633_write_table!
[ 339.358271] vi vi.0: CSI_A syncpt timeout, syncpt = 6, err = -11
[ 339.365539] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 339.374458] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 339.379993] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 339.385223] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 339.390940] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 339.396071] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 339.401237] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 339.407051] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 339.412953] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 339.418018] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 339.623110] vi vi.0: CSI_A syncpt timeout, syncpt = 7, err = -11
[ 339.630189] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 339.636191] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 339.641775] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 339.647202] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 339.652700] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 339.657648] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 339.662521] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 339.668473] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 339.674233] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 339.679324] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 339.884269] vi vi.0: CSI_A syncpt timeout, syncpt = 8, err = -11
[ 339.892978] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 339.905089] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 339.909986] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 339.915230] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 339.920154] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 339.925071] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 339.929990] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 339.935677] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 339.941336] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 339.946514] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 340.150747] vi vi.0: CSI_A syncpt timeout, syncpt = 9, err = -11
[ 340.158091] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 340.166325] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 340.173220] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 340.178169] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 340.183517] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 340.188456] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 340.193705] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 340.199364] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 340.205196] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 340.210174] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 340.414544] vi vi.0: CSI_A syncpt timeout, syncpt = 10, err = -11
[ 340.421846] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 340.427214] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 340.432831] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 340.439079] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 340.448793] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 340.453861] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 340.459006] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 340.464682] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 340.470540] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 340.475926] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 340.680387] vi vi.0: CSI_A syncpt timeout, syncpt = 11, err = -11
[ 340.688649] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 340.698815] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 340.703922] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 340.709593] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 340.714636] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 340.719542] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 340.724689] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 340.730412] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 340.736308] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 340.741255] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 340.945280] vi vi.0: CSI_A syncpt timeout, syncpt = 12, err = -11
[ 340.957978] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 340.966734] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 340.973500] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 340.979856] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 340.986948] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 340.992032] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 340.997083] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 341.003204] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 341.008834] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 341.013995] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 341.219071] vi vi.0: CSI_A syncpt timeout, syncpt = 13, err = -11
[ 341.236002] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 341.243104] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 341.249034] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 341.253989] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 341.258989] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 341.264020] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 341.268998] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 341.274628] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 341.280364] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 341.285584] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
select timeout
[ 341.490095] vi vi.0: CSI_A syncpt timeout, syncpt = 14, err = -11
[ 341.499697] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 341.511183] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 341.516150] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 341.521200] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 341.526082] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 341.531417] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 341.536334] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 341.542152] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 341.547806] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 341.552910] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 341.757583] vi vi.0: CSI_A syncpt timeout, syncpt = 15, err = -11
[ 341.764596] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 341.770767] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 341.780084] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 341.785475] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 341.790945] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 341.796159] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 341.801196] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 341.806871] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 341.812884] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 341.818004] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 342.032510] vi vi.0: CSI_A syncpt timeout, syncpt = 16, err = -11
[ 342.040501] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 342.048924] TEGRA_CSI_CSI_CILA_STATUS 0x00000001
[ 342.059977] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 342.065611] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 342.070519] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 342.075484] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 342.080416] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 342.086259] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 342.092217] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 342.097209] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
Please help to confirm the debug message. We used oscilloscope to check MIPI CSI_A_CLK(120MHz), CSI_A_D0/1, CSI_B_D0/1 signal is working but TK1 CSI_A syncpt timeout.
If available, please support any suggestion or direction to overcome this issue. Any help will be sincerely appreciated. Thanks.