CSI skipping every other frame unless removing SINGLESHOT bit

[urielom8ug]

I have an FPGA connected to a TI radar that sends the data as 4096x64 RAW10 frames.
I am running JetPack 4.6.4 on TX2 NX.

Data is sent from the FPGA (Lattice crosslink) via two lanes with 850mbps (total 1900mbps, lane frequency 425mhz)

Data is sent as 10fps, every frame is generated very quickly (few ms) and then there is a quiet period rounding to 100ms.

I am using v4l2-ctl to read the frames, I am getting 5fps very stable.

Follow this post:

Only each of the second frame is captured on the CSI bus

@ShaneCCC , thanks a lot for the patch. We could get 60 fps with it and now it is under the testing. But I have some questions regarding SINGLESHOT. So as I understand - with SINGLESHOT bit - VI channel is disabled automatically after FE packet. For reenabling - ENABLE bit needs to be set again on the next frame. Without SINGLESHOT - VI channel is always enabled and looks like that’s why it stopped missing frames. From other hand - there is some kind of warning in TRM: “The SINGLESHOT bit, i…

I patched the kernel to disable singleshot bit and now I am getting 10fps.

While it works I don’t like to patch this as I also have a camera on another CSI port.

What I like to understand is the reason for this issue so I can workaround it.

Doesn’t seem to be related to fps, if I change my sending to 300ms instead of 3.3fps I get exactly 1.66fps which is half.

What are the conditions that triggers this bug?

[ShaneCCC]

Could you check if can increase VSYNC blanking period to try.

[urielom8ug]

By VSYNC blanking you mean time between frames?

Even when sending a frame every 300ms it happens, it is exactly half the rate. doesn’t matter if I send every 100ms or 300ms I see every other frame.

Can you please answer what is the reason for the SINGLESHOT bit and what triggers this issue? It doesn’t seem to be related to frame rate or idle period between the frames

[ShaneCCC]

If the second FS too early to catch this kind of issue would be happened.

Thanks

[urielom8ug]

What is the definition of too early?

Does the CSI/VI schedules a turn on of the HW based on some calcluation? can you explain the EXACT conditions for this and how to calculate it?

If I understand this then I can work on working around this, right now as I said 100ms or 300ms between FS causes the same issue and removing SINGLESHOT fixes the issue.

Without SINGLESHOT my understanding is the HW is always ON so it doesn’t misses the frame but this is not the default and can cause errors (per the TRM).

[ShaneCCC]

If the sensor send FS before the driver trigger the SINGLESHOT then this frame will be lost.

Thanks

[urielom8ug]

But when does the driver sends/schedules it? based on what?

[ShaneCCC]

You can check the vi4_fops.c to know the detail.