cudaHostRegister not supported

Robotics & Edge Computing Jetson Systems Jetson Nano
1

I have software that calls cudaHostRegister on an mmapped memory chunk with flag cudaHostRegisterMapped.
It works on the TX2 and Xavier AGX boards, but crashes with cudaErrorNotSupported on the Nano.

However, I had them run the deviceQuery sample and it appears the device supports the feature:

Support host page-locked memory mapping:       Yes

Does that feature not correspond to cudaHostRegister()?

3

At the same JetPack version? What’s the Cuda version?
Got to know if it’s related with the GPU arch.

4

@kayccc
Thank you for the response, I forgot to check back in here.

Nano:
Cuda version is 10.2, code is compiled for arch 5.3.
/etc/nv_tegra_release: # R32 (release), REVISION: 7.1, GCID: 29818004, BOARD: t210ref, EABI: aarch64, DATE: Sat Feb 19 17:05:08 UTC 2022

Xavier:
Cuda 10.2, code for arch 7.2
/etc/nv_tegra_release: # R32 (release), REVISION: 4.3, GCID: 21589087, BOARD: t186ref, EABI: aarch64, DATE: Fri Jun 26 04:34:27 UTC 2020

Full output of Nano deviceQuery:

Device 0: "NVIDIA Tegra X1"
  CUDA Driver Version / Runtime Version          10.2 / 10.2
  CUDA Capability Major/Minor version number:    5.3
  Total amount of global memory:                 3956 MBytes (4148273152 bytes)
  ( 1) Multiprocessors, (128) CUDA Cores/MP:     128 CUDA Cores
  GPU Max Clock rate:                            922 MHz (0.92 GHz)
  Memory Clock rate:                             13 Mhz
  Memory Bus Width:                              64-bit
  L2 Cache Size:                                 262144 bytes
  Maximum Texture Dimension Size (x,y,z)         1D=(65536), 2D=(65536, 65536), 3D=(4096, 4096, 4096)
  Maximum Layered 1D Texture Size, (num) layers  1D=(16384), 2048 layers
  Maximum Layered 2D Texture Size, (num) layers  2D=(16384, 16384), 2048 layers
  Total amount of constant memory:               65536 bytes
  Total amount of shared memory per block:       49152 bytes
  Total number of registers available per block: 32768
  Warp size:                                     32
  Maximum number of threads per multiprocessor:  2048
  Maximum number of threads per block:           1024
  Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
  Max dimension size of a grid size    (x,y,z): (2147483647, 65535, 65535)
  Maximum memory pitch:                          2147483647 bytes
  Texture alignment:                             512 bytes
  Concurrent copy and kernel execution:          Yes with 1 copy engine(s)
  Run time limit on kernels:                     Yes
  Integrated GPU sharing Host Memory:            Yes
  Support host page-locked memory mapping:       Yes
  Alignment requirement for Surfaces:            Yes
  Device has ECC support:                        Disabled
  Device supports Unified Addressing (UVA):      Yes
  Device supports Compute Preemption:            No
  Supports Cooperative Kernel Launch:            No
  Supports MultiDevice Co-op Kernel Launch:      No
  Device PCI Domain ID / Bus ID / location ID:   0 / 0 / 0
  Compute Mode:
     < Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >
deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 10.2, CUDA Runtime Version = 10.2, NumDevs = 1
Result = PASS
6

Hi,

cudaHostRegister() requires the I/O coherency feature which is avaialable from Xavier.
You can check if a device has this support by the cudaDevAttrHostRegisterSupported attribute.

The attribute below indicates the capability for a pinned host memory.

Support host page-locked memory mapping:       Yes

You can find more information in our document:

Thanks.