Device tree overlay for PPS support on jp 6.2.1

Robotics & Edge Computing Robotics - Isaac Isaac ROS
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1

Hi!

I have the same problem as @roo from this thread:

I’m not so knowledgeable on Device tree overlays so don’t be hard on me please. ;)

I’m setting up a test rig where I need precise timing under linux / ROS2.

The original forum post was for JP4.6.4 but since than lot has changed and the example doesn’t work for me, plus my board is different a Nano Super.

As I’m not deep in the subject I also tried ChatGPT maybe it can give me suggestions but as you can imagine it miserably failed. After reading through the topics here in the forum I came to the conclusion that the last thing I can do is ask you guys, maybe sombody could help.

If we find the solution, I’ll post my findings too.

Thaks in advance!

Lehel

2

Hello @lelehel !

Can you share your current overlay file?

For Jetson Orin Nano developer kit carrier board Pin 7 of J41 Expansion header is PAC.06.
GPIO09

Try using this in your overlay file:
gpios = <&tegra_main_gpio TEGRA234_MAIN_GPIO(AC, 6) GPIO_ACTIVE_HIGH>;

Please verify the phandle name&tegra_main_gpio.

Nico
Best regards
Embedded Software Engineer at ProventusNova

3

Hi,

Thank you for your fast reply!

Let’s assume I have no overlay file. What I have tried is Roo’s from the mentioned thread:

/dts-v1/;
/plugin/;

/ {
overlay-name = “PPS Overlay”;
jetson-header-name = “Jetson 40pin Header”;
compatible = “nvidia,p3449-0000-b00+p3448-0000-b00”;

fragment@0 {
    target-path = "/";
    __overlay__ {
        pps_gpio {
            compatible = "pps-gpio";
            gpios = <0x5b 0xd8 0x0>;
            status = "okay";
        };
    };
};

};

Here are my board infos, I hope I executed the right commands:

cat /proc/device-tree/compatible
nvidia,p3768-0000+p3767-0005-supernvidia,p3767-0005nvidia,tegra234

find /sys/firmware/devicetree/base -type d -name “gpio@*”
/sys/firmware/devicetree/base/bus@0/gpio@2200000
/sys/firmware/devicetree/base/bus@0/gpio@c2f0000

hexdump -e ‘1/4 “0x%08x\n”’ /sys/firmware/devicetree/base/bus@0/gpio@2200000/phandle
0xf3000000

L.

4

Hi!

I would try this:

/dts-v1/;
/plugin/;
 
/ {
    overlay-name = "My PPS Overlay";
    jetson-header-name = "Jetson 40pin Header";
    ccompatible = "nvidia,p3768-0000+p3767-0005-super", "nvidia,p3767-0005", "nvidia,tegra234";
 
    fragment@0 {
		target-path = "/";
		__overlay__ {
			pps_gpio {
				compatible = "pps-gpio";
				gpios = <&tegra_main_gpio TEGRA234_MAIN_GPIO(AC, 6) GPIO_ACTIVE_HIGH>;
				assert-falling-edge;
				status = "okay";
			};
		};
	};
};

To add the gpios with hexadecimal values: (20*8) + 6 = 166 = 0xa6

#define TEGRA234_MAIN_GPIO_PORT_AC 20

#define TEGRA234_MAIN_GPIO(port, offset) \
    ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset)

gpio active high: 0x0

#define GPIO_ACTIVE_HIGH 0
#define GPIO_ACTIVE_LOW 1

For the phandle value, decompile your DTB file and look for it under the correct gpio node.
I also found this: PPS on Jetson Orin Nano DevKit which may help you enabling PPS support.

Nico
Best regards
Embedded Software Engineer at ProventusNova

5

I’m back,

I had time for a little trial&error, mostly error :(

/dts-v1/;
/plugin/;

/ {
overlay-name = “PPS Overlay”;
jetson-header-name = “Jetson 40pin Header”;
compatible = “nvidia,p3768-0000+p3767-0005-super”, “nvidia,p3767-0005”, “nvidia,tegra234”;

fragment@0 {
    target-path = "/chosen";
    __overlay__ {
        pps {
            compatible = "pps-gpio";
            gpios = <&tegra_main_gpio 134 0x0>; 
            status = "okay";
        };
    };
};

};

Also I tried this but didn’t even compile, so I went back to “&tegra_main_gpio”

/dts-v1/;
/plugin/;

/ {
overlay-name = “PPS Overlay”;
jetson-header-name = “Jetson 40pin Header”;
compatible = “nvidia,p3768-0000+p3767-0005-super”, “nvidia,p3767-0005”, “nvidia,tegra234”;

fragment@0 {
    target-path = "/chosen";
    __overlay__ {
        pps {
            compatible = "pps-gpio";
            gpios = <0xf3 134 0x0>; 
            status = "okay";
        };
    };
};

};

Either way, boot failed had to revert.

phandle

&0xf3

hexdump -e ‘1/4 “0x%08x\n”’ /sys/firmware/devicetree/base/bus@0/gpio@2200000/phandle
…returned 0xf3000000
”Due to an endianness difference between how the device tree stores the value (big-endian) and how the system reads it (little-endian), this output confirms that the correct phandle is 0xf3"

**Pin number 134 for pin31. **
On the Jetson Orin Nano developer kit carrier board, physical pin 31 is connected to the GPIO signal named PQ.06.

The numeric offset is calculated as (port_index * 8) + pin_index. For pin 31 (PQ.06), the calculation is (16 * 8) + 6 = 134.

Tem me If I do anything wrong! ;)

Thanks!

6

Hi @lelehel,

Taking roo’s post as reference, they target Pin 7 of the Jetson Nano developer kit which is an audio master clock. For Jetson Orin Nano developer kit, Pin 7 is also an audio master clock.

I would suggest trying:

gpios = <0xf3 0xa6 0x0>

To target pin 7 of the devkit.