In the past I’ve enabled PPS input on Pin 7 of the 40 pin GPIO header on a Jetson Nano (see forum thread here: Device Tree Overlay for PPS Support on JP4.6.4) and am attempting to port this to the Orin NX using the nVidia dev kit carrier board.
I had asked on the previous thread how to determine the pin hex codes as functions such as TEGRA234_MAIN_GPIO(AC, 6) and definitions such as GPIO_ACTIVE_HIGH are not available when creating a .dts and not recompiling the kernel, but I didn’t receive an answer and I’m facing the same problem again. I’ve searched for similar threads for the Orin NX but haven’t been able to find an answer.
Here is the current state of the .dts for the overlay, I’ve copied in 0xd8 for the gpio address value from the Nano overlay but would like to replace that with the correct value for pin 7 on the Orin NX 40 pin header. How can I determine its hex code (or import the function TEGRA234_MAIN_GPIO)?
Note that I copied in the symbols and definitions of tegra_main_gpio from the decompiled /proc/device-tree in an attempt to get the &tegra_main_gpio part to work, which did succeed!
Have you tried to download the kernel source and add them in device tree source instead of creating overlay package?
In this way, you don’t need to care about the hex value.
I’ve not tried that as my application requirement is that I can apply this as an overlay to the unmodified distribution of the OS provided by nVidia. What’s the best way to look the values up? Surely each GPIO pin has a fixed hex value/index?
If I did take the kernel mod route, could I compile the kernel/device tree then just copy paste the hex values that get generated into my overlay?
Hi Kevin,
I’m trying to build this overlay for JP 5.1.2.
Would /proc/device-tree be the right place to look at for comparing other nodes? I wasn’t able to find any reference to the GPIO pins in there myself.
Hi Kevin,
I found the following in the extracted_proc.dts file from your previous post, this does yield a reference for tegra_main_gpio but not a definition of the function that is generally referenced in other posts. The reference does provide a range of hex values but doesn’t provide me any clues as to what the hex value is for the pin I want to use. Is there a way to figure out what the address is for any given GPIO pin from this output?
From this it appears possible to calculate the pin address if the port and offset are known.
I found the following in hardware\nvidia\soc\tegra\kernel-include\dt-common\jetson\tegra234-p3767-0000-common.h
#define HDR40_PIN7_GPIO TEGRA_MAIN_GPIO(AC, 6)
This would indicate that the pin is on port AC offset 6. My only challenge now is finding the definition of port AC, as it’s not in the list from tegra186-gpio.h or any other files within the source package. Can you point me in the right direction there?
I may have posted too soon as I didn’t realize I was incorrectly searching for TEGRA_MAIN_GPIO instead of TEGRA234_MAIN_GPIO. Searching the correct function yields the following from tegra234-gpio.h.
Unfortunately this does not work. The following is added into the dtb when I run fdtdump /boot/kernel_tegra234-p3767-0000-p3768-0000-a0-user-custom.dtb after applying the overlay, however no pps device is created at /dev/pps*. Any thoughts Kevin?
This appears correct, the 0x50 address is the phandle of &tegra_main_gpio, the only thing I can think of is that the pin address is still incorrect. Here is a dump from dmesg indicating the issue:
[ 1.629970] pps_core: LinuxPPS API ver. 1 registered
[ 1.634931] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 4.513018] pps-gpio pps_gpio: failed to request PPS GPIO
[ 4.518564] pps-gpio: probe of pps_gpio failed with error -22
I don’t think the pin number is what we want here, I’m looking for the pin address which for AC6 is calculated with the TEGRA234_MAIN_GPIO() function in the kernel source.
Just to be sure I did try the pin number (492/0x1EC) and it did not work either.
It appears that the kernel for JP 5.1.2 has a loading order issue that prevents the PPS module from being loaded, best guess is the GPIOs aren’t registered yet at that point in the boot.
I therefore retried the same test on JP 6.0.2 and the PPS overlay works perfectly using the math/functions I determined from the kernel source header files. This appears to confirm that the issue is inerrant to the specific kernel build for JP 5.1.2. Rebuilding my own kernel for that version, or just using a newer JP release seem to be the only options unless someone else can make another suggestion as to loading the PPS module after the GPIOs are available.
I was successful using JP 6.0 (which is listed in the SDK Manager as “Jetpack 6.0 (Rev2)” hence why I called it 6.0.2).
There is a warning generated when I create the dtbo related to &tegra_main_gpio being undefind, however since it’s defined in the Jetpack kernel device tree when the overlay is applied this reference can still be found.
There appears to be a device registered at /dev/pps0 in the newer Jetpacks (6.0+) even before I have applied my overlay. This device appears to work as a PPS source (ppstest /dev/pps0 shows a 1Hz signal) but I’m assuming this is generated internally to the Jetson since I haven’t applied my overlay yet.
After my overlay is applied, no additional PPS sources are registered (there is no /dev/pps1 for example) and when my PPS source is disconnected from the GPIO I’m using /dev/pps0 doesn’t stop producing a signal. Therefore it’s not actually working.
Can you provide details on where this PPS source is coming from and how it’s configured in JP6.0+? I’m wondering if this is causing my overlay not to function or be applied.
I’ve also noticed that the way overlays are applied with /opt/nvidia/jetson-io/config-by-hardware.py appears to have changed in JP6.0+. Previously a user-custom dtb was generated, now however only extlinux.conf is modified to add an OVERLAYS section to the config. With this method, when I extract the /proc/device-tree my overlay is not present on JP6.0+. Can you point me in the right direction for applying overlays in new Jetpack?
It appears the phandle &tegra_main_gpio was renamed in JP 6.0+ to just &gpio. With this changed in the overlay file I do see a second pps device registered and it is functional when my PPS source is connected.