DGX Spark P4242 ConnectX-7 — SyncE unavailable: MCAM synce_registers=0, no mlx5 DPLL device (PSID NVD0000000087)

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1

We are integrating NVIDIA DGX Spark with OCUDU as an O-RAN Distributed Unit (O-DU). Our deployment requires Synchronous Ethernet (SyncE) frequency synchronization through the ConnectX-7 Ethernet interface.

We would like to confirm whether native SyncE is supported on DGX Spark and, if so, how to configure and enable it.

  1. Is synce_registers=0 expected for PSID NVD0000000087 with firmware 28.45.4028? Is this a deliberate restriction, a firmware limitation, or a hardware limitation?
  2. Does NVIDIA officially support native SyncE/EEC locking on the P4242 ConnectX-7? If yes, which DGX Spark-qualified firmware and software versions expose the required MCAM and DPLL capabilities, and what is the supported configuration procedure?
  3. If unsupported, is there an approved alternative for an O-RAN DU requiring SyncE? Please distinguish PTP time synchronization from Ethernet frequency locking.

Additional info:

**1. Hardware and software configuration**

  • Platform: NVIDIA DGX Spark P4242
  • Network adapter: NVIDIA ConnectX-7
  • Firmware PSID: NVD0000000087
  • Firmware version: 28.45.4028
  • Operating system: Ubuntu 24.04.5 LTS (ARM64)
  • Kernel: 7.0.0-1019-nvidia
  • Network driver: mlx5_core
  • Kernel configuration: CONFIG_DPLL=y, CONFIG_MLX5_DPLL=m
  • NVIDIA MFT version: 4.35.0.159-1

**2. Current synchronization setup**

The DGX Spark is connected through a 10 GbE fiber link to an external GNSS-locked telecom timing switch providing IEEE 1588 PTP and SyncE.

PTP synchronization works successfully using LinuxPTP:

  • PTP profile: ITU-T G.8275.1-derived configuration
  • PTP domain: 24
  • Transport: Layer 2 Ethernet
  • Hardware timestamping: Enabled
  • PTP state: SLAVE
  • Observed PTP RMS offset: approximately 1–3 ns
  • Linux system clock synchronized using phc2sys

We also confirmed that SyncE ESMC frames are received from the timing switch.

However, we cannot establish or verify native SyncE frequency lock on the ConnectX-7.

**3. Firmware capability investigation**

The Linux kernel includes the mlx5_dpll driver, but no DPLL auxiliary device is registered.

We queried the ConnectX-7 MCAM capability register using NVIDIA MFT:

Command:

`mlxreg -d 0000:01:00.0 --reg_name MCAM --get --indexes “access_reg_group=0x2,feature_group=0x0”`

Relevant result:

  • access_reg_group: 0x00000002
  • mng_access_reg_cap_mask[1]: 0x00020000
  • synce_registers capability field: 0 (based on Linux mlx5 register definitions)

The same result was obtained from PCI function 0002:01:00.0.

This suggests that firmware version 28.45.4028 does not expose the SyncE registers required by the Linux mlx5 DPLL driver.

2

Considering how cut down the CX-7 feature set is in the Spark I wouldn’t expect it.