Display Issue after Updating to L4T 35.6.0

joseph.zc · February 13, 2025, 6:29am

We had to flash our Jetsons for compatibility with L4T 35.6.0. We previously used 35.4.1 without any display issues, but with 35.6.0, I am finding that the Jetson cannot connect to the touch panel monitors that we’ve bought. The panels are 1024x600 in resolution, and while it was fine with 35.4.1, when booting with it connected with 35.6.0, the screen shows the UEFI splash screen but instead of going to the dmesg printout and login screen, it just sort of flickers and shows random lines vertically.

Based on the reply I received here.
It does seem to line up with the issues mentioned on this NVIDIA page

Assuming it is in fact a frame buffer console pixel clock calculation issue, what can be done? I tried using the script mentioned in the article and flashing again, but the result was the same with the resolution set to 720x480 and 1024x600. I have contacted the makers of the touch panel to see if they can provide things like the porch and sync parameters to see if that works, but in the meanwhile, if anyone has any other ideas, feel free to let me know.

Here is the dmesg output for | grep display since --level=err only showed display-related issues (and an unrelated error regarding imx219, but I don’t think it matters).

[    0.980810] tegradccommon 15200000.display-hub: Nvhost Channel map failed
[    5.823001] tegradc 15200000.display: Adding to iommu group 26
[    5.823358] tegradccommon 15200000.display-hub: host1x channel mapped
[    5.823372] tegradccommon 15200000.display-hub: dc_common syncpt # 1 allocated
[    5.823405] tegradc 15210000.display: Adding to iommu group 26
[    5.823409] tegradccommon 15200000.display-hub: dma mapping done
[    5.825434] tegradc 15210000.display: disp0 connected to head1->sor
[    5.825499] tegradc 15210000.display: parse_dp_settings: No dp-lt-settings node
[    5.825594] tegradc 15210000.display: DT parsed successfully
[    5.825600] tegradc 15210000.display: dc.1 probe not in device tree order, deferring
[    5.827512] tegradc 15200000.display: disp0 connected to head0->sor1
[    5.860438] tegradc 15200000.display: DT parsed successfully
[    5.860471] tegradc 15200000.display: Display dc.0000000009228150 registered with id=0
[    5.899683] tegradc 15200000.display: vblank syncpt # 8 for dc 0
[    5.909247] tegradc 15200000.display: vpulse3 syncpt # 9 for dc 0
[    5.922284] tegradc 15200000.display: hdmi: can't get adpater for ddc bus 3
[    5.933614] tegradc 15200000.display: out->type:1 out_ops->init err = -517
[    6.268225] tegradc 15210000.display: disp0 connected to head1->sor
[    6.272902] tegradc 15210000.display: parse_dp_settings: No dp-lt-settings node
[    6.286644] tegradc 15210000.display: DT parsed successfully
[    6.300060] tegradc 15210000.display: dc.1 probe not in device tree order, deferring
[    6.314296] tegradc 15200000.display: disp0 connected to head0->sor1
[    6.338305] tegradc 15200000.display: DT parsed successfully
[    6.350193] tegradc 15200000.display: Display dc.0000000079a50ac3 registered with id=0
[    6.425969] tegradc 15200000.display: vblank syncpt # 11 for dc 0
[    6.438685] tegradc 15200000.display: vpulse3 syncpt # 12 for dc 0
[    6.445978] tegradc 15200000.display: hdmi: invalid prod list prod_list_hdmi_board
[    6.457057] tegradc 15200000.display: hdmi: tegra_hdmi_tmds_range_read(bd) failed
[    6.477065] tegradc 15200000.display: probed
[    6.528811] tegradc 15200000.display: fb registered
[    6.611911] tegradc 15200000.display: dc_poll_register 0x41: timeout
[    6.620083] tegradc 15200000.display: timeout waiting for postcomp init state to promote
[    6.671907] tegradc 15200000.display: dc_poll_register 0x41: timeout
[    6.682292] tegradc 15200000.display: timeout waiting for win assignments to promote
[    6.682298] tegradc 15200000.display: tegra_nvdisp_head_enable, failed head enable
[    6.682452] tegradc 15210000.display: disp1 connected to head1->sor
[    6.694684] tegradc 15210000.display: parse_dp_settings: No dp-lt-settings node
[    6.694759] tegradc 15210000.display: DT parsed successfully
[    6.708703] tegradc 15210000.display: Display dc.0000000074f293b5 registered with id=1
[    6.743781] tegradc 15210000.display: vblank syncpt # 17 for dc 1
[    6.743793] tegradc 15210000.display: vpulse3 syncpt # 18 for dc 1
[    6.750408] tegradc 15210000.display: probed
[    6.827046] tegradc 15210000.display: fb registered
[    6.860586] tegradc 15200000.display: blank - powerdown
[    6.864844] tegradc 15200000.display: unblank
[    6.919901] tegradc 15200000.display: dc_poll_register 0x41: timeout
[    6.919906] tegradc 15200000.display: dc timeout waiting for DC to stop
[    6.971901] tegradc 15200000.display: dc_poll_register 0x41: timeout
[    6.971906] tegradc 15200000.display: dc timeout waiting for DC to stop
[    7.023903] tegradc 15200000.display: dc_poll_register 0x41: timeout
[    7.023909] tegradc 15200000.display: timeout waiting for postcomp init state to promote
[    7.075904] tegradc 15200000.display: dc_poll_register 0x41: timeout
[    7.075910] tegradc 15200000.display: timeout waiting for win assignments to promote
[    7.075914] tegradc 15200000.display: tegra_nvdisp_head_enable, failed head enable
[    7.075938] tegradc 15200000.display: update windows ret = -14
[    7.075942] tegradc 15200000.display: sync windows ret = -14
[    7.126327] tegradc 15210000.display: blank - powerdown
[    7.178701] tegradc 15200000.display: hdmi: plugged
[   23.850351] tegradc 15200000.display: blank - powerdown
[   23.850387] tegradc 15200000.display: unblank
[   23.899970] tegradc 15200000.display: dc_poll_register 0x41: timeout
[   23.899979] tegradc 15200000.display: dc timeout waiting for DC to stop
[   23.952072] tegradc 15200000.display: dc_poll_register 0x41: timeout
[   23.952080] tegradc 15200000.display: dc timeout waiting for DC to stop
[   24.003924] tegradc 15200000.display: dc_poll_register 0x41: timeout
[   24.003996] tegradc 15200000.display: timeout waiting for postcomp init state to promote
[   24.055929] tegradc 15200000.display: dc_poll_register 0x41: timeout
[   24.055940] tegradc 15200000.display: timeout waiting for win assignments to promote
[   24.055945] tegradc 15200000.display: tegra_nvdisp_head_enable, failed head enable
[   24.057652] tegradc 15200000.display: unblank
[   24.107945] tegradc 15200000.display: dc_poll_register 0x41: timeout
[   24.107952] tegradc 15200000.display: dc timeout waiting for DC to stop
[   24.159923] tegradc 15200000.display: dc_poll_register 0x41: timeout
[   24.159931] tegradc 15200000.display: dc timeout waiting for DC to stop
[   24.211951] tegradc 15200000.display: dc_poll_register 0x41: timeout
[   24.211961] tegradc 15200000.display: timeout waiting for postcomp init state to promote
[   24.263929] tegradc 15200000.display: dc_poll_register 0x41: timeout
[   24.263940] tegradc 15200000.display: timeout waiting for win assignments to promote
[   24.263944] tegradc 15200000.display: tegra_nvdisp_head_enable, failed head enable
[   24.266911] tegradc 15210000.display: blank - powerdown
[  343.242998] tegradc 15200000.display: blank - powerdown
[  343.243018] tegradc 15210000.display: blank - powerdown

Thank you

WayneWWW · February 13, 2025, 7:43am

Please check if this issue would only be reproduced if you connect the monitor and boot.

For example, if you hotplug the monitor after system is up, then whether it could work or not.
I mean connect no monitor during boot.

joseph.zc · February 13, 2025, 8:02am

I had not considered that, but it does show the desktop normally if I boot without the cable connected and then connect afterwards.

It seems the issue only occurs when the 1024x600 display is connected on boot.

WayneWWW · February 13, 2025, 8:21am

please check if disabling seamless and add patch would help or not.

https://docs.nvidia.com/jetson/archives/r35.6.0/DeveloperGuide/SD/Kernel/DisplayConfigurationAndBringUp/XavierDisplayconfig.html?highlight=seamless#bypassing-the-seamless-display-issue

joseph.zc · February 19, 2025, 4:54am

I tried that but it still doesn’t seem to work. However, the way I do it might have been incorrect. This was my process after applying the two patches mentioned in that link.

cd Linux_for_Tegra/source/public/kernel/kernel-5.10
export PATH=~/gcc_bin/bin/:$PATH
export CROSSBIN=aarch64-buildroot-linux-gnu-
export CROSS_COMPILE=${CROSSBIN}
export ARCH=arm64
make O=./kernel_build_out tegra_defconfig
make O=./kernel_build_out/ dtbs
make O=./kernel_build_out/ modules
make O=./kernel_build_out/ Image
./nvbuild.sh -o ./kernel/kernel-5.10/kernel_build_out/
sudo cp kernel/kernel-5.10/kernel_build_out/arch/arm64/boot/Image ~/l4t_35_6_0/Linux_for_Tegra/kernel/
cp kernel/kernel-5.10/kernel_build_out/arch/arm64/boot/dts/nvidia/tegra194-p3668-0001-p3509-0000.dtb ~/l4t_35_6_0/Linux_for_Tegra/kernel/dtb/
sudo ./flash.sh jetson-xavier-nx-devkit-emmc mmcblk0p1

I also received the display specs from Matrix Orbital and applied the nv-enable-hard-coded-kernel-boot-display-mode.sh patch, but it was not successful either with or without the above patches applied.

fbcon_node="/host1x/sor2/hdmi-display/nvidia,fbcon-default-mode"
properties=(
	"clock-frequency:51000000"
	"hactive:1024"
	"vactive:600"
	"hfront-porch:140"
	"hback-porch:140"
	"hsync-len:20"
	"vfront-porch:12"
	"vback-porch:23"
	"vsync-len:3"
	"nvidia,h-ref-to-sync:1"
	"nvidia,v-ref-to-sync:1"
	"flags:0x00000003"
	"vmode:0x00400000"
)

WayneWWW · February 19, 2025, 9:02am

May I confirm which patch are you applying?
No need to try nv-enable-hard-coded-kernel-boot-display-mode.sh. It is not related.

joseph.zc · February 19, 2025, 4:19pm

The patches from this link that you replied with

I tried with just disable seamless and with both disable seamless and power domains set to always on applied, but like I said in my reply, I’m not sure if copying the Image and dtb files were enough to apply them before flashing.

WayneWWW · February 19, 2025, 4:38pm

Just to clarify. Is this on NV devkit or your custom board?

joseph.zc · February 20, 2025, 3:31pm

I believed it was a devkit, but it is this board from Aetina.

WayneWWW · February 20, 2025, 4:02pm

Please check if Aetina provides any custom BSP for this board.

It is a custom board which we don’t know how it hardware is designed.

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Display Issue after Updating to L4T 35.6.0

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