No, 15210000 is the one unplugged. When I plug in the other display it displays correctly:
[ 471.075327] tegradc 15210000.display: dp: plug event received
[ 471.075452] hpd: state 3 (Disabled), hpd 1, pending_hpd_evt 1
[ 471.075549] hpd: switching from state 3 (Disabled) to state 0 (Reset)
[ 471.176409] hpd: state 0 (Reset), hpd 1, pending_hpd_evt 0
[ 471.176509] tegradc 15210000.display: blank - powerdown
[ 471.176643] extcon-disp-state external-connection:disp-state: cable 44 state 0 already set.
[ 471.176653] Extcon DP: HPD disabled
[ 471.176662] hpd: switching from state 0 (Reset) to state 1 (Check Plug)
[ 471.176685] hpd: state 1 (Check Plug), hpd 1, pending_hpd_evt 0
[ 471.176695] hpd: switching from state 1 (Check Plug) to state 2 (Check EDID)
[ 471.180626] tegradc 15200000.display: blank - powerdown
[ 471.180664] tegradc 15210000.display: blank - powerdown
[ 471.184680] hpd: state 2 (Check EDID), hpd 1, pending_hpd_evt 0
[ 471.190694] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 471.266720] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd
[ 471.266951] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd
[ 471.267177] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd
[ 471.274242] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 471.284780] dp lt: state 0 (Reset), pending_lt_evt 1
[ 471.284789] dp lt: switching from state 0 (Reset) to state 0 (Reset)
[ 471.284797] dp lt: state 0 (Reset), pending_lt_evt 0
[ 471.286267] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[ 471.286277] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 471.286522] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 471.286530] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 471.286537] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 471.286545] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 471.286552] dp lt: tx_pu: 0x20
[ 471.287506] dp lt: CR not done
[ 471.287972] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 471.287977] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 471.287981] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 471.287985] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 471.287989] dp lt: CR retry
[ 471.287993] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 471.288001] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 471.288011] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 471.288018] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 471.288025] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 471.288031] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 471.288037] dp lt: tx_pu: 0x30
[ 471.291079] dp lt: CR done
[ 471.291087] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[ 471.291096] dp lt: state 3 (channel equalization), pending_lt_evt 0
[ 471.293634] dp lt: CE done
[ 471.293641] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[ 471.293947] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 471.294190] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.294429] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.294666] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.294903] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.295167] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.295411] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.295649] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.295886] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.296125] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.296383] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.296878] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.297124] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.297144] tegradc 15210000.display: blank - powerdown
[ 471.327704] dp lt: state 5 (link training pass), pending_lt_evt 1
[ 471.327709] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[ 471.327714] dp lt: state 0 (Reset), pending_lt_evt 0
[ 471.327721] dp lt: link training force disable
[ 471.327725] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[ 471.350827] tegra_nvdisp_handle_pd_disable: Powergated Head2 pd
[ 471.351002] tegra_nvdisp_handle_pd_disable: Powergated Head1 pd
[ 471.351913] tegra_nvdisp_handle_pd_disable: Powergated Head0 pd
[ 471.352222] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 471.352235] tegradc 15210000.display: unblank
[ 471.353699] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd
[ 471.353882] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd
[ 471.354101] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd
[ 471.358808] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 471.368525] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[ 471.368530] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[ 471.368536] dp lt: state 0 (Reset), pending_lt_evt 0
[ 471.369988] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[ 471.369994] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 471.370231] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 471.370237] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 471.370243] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 471.370268] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 471.370274] dp lt: tx_pu: 0x20
[ 471.371205] dp lt: CR done
[ 471.371209] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[ 471.371214] dp lt: state 3 (channel equalization), pending_lt_evt 0
[ 471.373675] dp lt: CE done
[ 471.373680] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[ 471.374031] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 471.374338] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.374626] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.374867] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.375105] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.375346] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.375584] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.375843] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.376083] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.376369] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.376917] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.377246] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.377490] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.377497] tegradc 15210000.display: blank - powerdown
[ 471.407364] dp lt: state 5 (link training pass), pending_lt_evt 1
[ 471.407389] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[ 471.407394] dp lt: state 0 (Reset), pending_lt_evt 0
[ 471.407399] dp lt: link training force disable
[ 471.407403] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[ 471.431423] tegra_nvdisp_handle_pd_disable: Powergated Head2 pd
[ 471.431597] tegra_nvdisp_handle_pd_disable: Powergated Head1 pd
[ 471.432679] tegra_nvdisp_handle_pd_disable: Powergated Head0 pd
[ 471.433048] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 471.433061] tegradc 15210000.display: unblank
[ 471.434663] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd
[ 471.435221] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd
[ 471.435637] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd
[ 471.441257] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 471.451765] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[ 471.451771] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[ 471.451778] dp lt: state 0 (Reset), pending_lt_evt 0
[ 471.453314] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[ 471.453326] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 471.453575] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 471.453584] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 471.453591] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 471.453598] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 471.453605] dp lt: tx_pu: 0x20
[ 471.454570] dp lt: CR done
[ 471.454576] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[ 471.454584] dp lt: state 3 (channel equalization), pending_lt_evt 0
[ 471.457492] dp lt: CE done
[ 471.457501] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[ 471.457734] extcon-disp-state external-connection:disp-state: cable 44 state 1
[ 471.457745] Extcon DP: HPD enabled
[ 471.457759] hpd: switching from state 2 (Check EDID) to state 4 (Enabled)
[ 471.458955] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 471.459235] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.459505] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.459768] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.460031] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.460288] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.460806] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.461123] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.461388] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.461647] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.461911] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.462175] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.462708] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[ 471.464581] tegradc 15200000.display: blank - powerdown
[ 471.464599] tegradc 15210000.display: blank - powerdown
[ 471.491100] dp lt: state 5 (link training pass), pending_lt_evt 1
[ 471.491106] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[ 471.491129] dp lt: state 0 (Reset), pending_lt_evt 0
[ 471.491139] dp lt: link training force disable
[ 471.491142] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[ 471.519996] tegra_nvdisp_handle_pd_disable: Powergated Head2 pd
[ 471.520568] tegra_nvdisp_handle_pd_disable: Powergated Head1 pd
[ 471.536739] tegra_nvdisp_handle_pd_disable: Powergated Head0 pd
[ 471.594917] tegradc 15210000.display: blank - powerdown
[ 471.595250] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 471.595304] tegradc 15210000.display: unblank
[ 471.596929] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd
[ 471.597673] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd
[ 471.597913] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd
[ 471.603766] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 471.613917] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[ 471.613924] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[ 471.613931] dp lt: state 0 (Reset), pending_lt_evt 0
[ 471.615412] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[ 471.615420] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 471.615664] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 471.615672] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 471.615679] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 471.615686] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 471.615692] dp lt: tx_pu: 0x20
[ 471.616696] dp lt: CR done
[ 471.616709] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[ 471.616717] dp lt: state 3 (channel equalization), pending_lt_evt 0
[ 471.619156] dp lt: CE done
[ 471.619163] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[ 471.619287] tegradc 15210000.display: unblank
[ 471.619322] tegradc 15200000.display: blank - powerdown
[ 472.036504] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 477.156485] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 482.276998] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 485.252932] start_addr=(0x20000), end_addr=(0x40000), buffer_size=(0x20000), smp_number_max=(16384)
[ 487.396522] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 492.516632] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 497.636447] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 502.757032] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 507.877419] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 512.996819] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 518.117095] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 523.236707] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 528.356516] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 533.476536] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[ 538.596506] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
The one that doesn’t work seems to be 15200000.