Dual Displayport issue with NX

Autonomous Machines Jetson & Embedded Systems Jetson Xavier NX
,
#1

Hello!

I am having problems with using two displayports on the new release (r35.1). I have ruled out hardware issues, as the system works with two displayports on an earlier release (r32).

We have two displayports on a custom carrier board, one connected to DP1 on the SOM, the other connected to DP0.
The one connected to DP-0 works as intended, but the one connected to DP-1 doesn’t work. Xrandr output however shows that dp-1 works and dp-0 is disconnected (Probably dp0 and 1 is switched in sw somewhere):

Screen 0: minimum 8 x 8, current 1920 x 1080, maximum 32767 x 32767
DP-0 disconnected (normal left inverted right x axis y axis)
DP-1 connected primary 1920x1080+0+0 (normal left inverted right x axis y axis) 530mm x 300mm
   1920x1080     60.00*+  74.98    59.95    50.00
   1680x1050     59.96
   1440x900      59.89
   1280x1024     75.03    60.00
   1280x960      60.00
   1280x720      60.00    59.94    50.00
   1024x768      75.03    70.07    60.01
   832x624       75.05
   800x600       75.00    72.19    60.32    56.25
   720x576       50.00
   720x480       59.94
   720x400       70.04
   640x480       75.00    72.81    67.06    59.94    59.94

I have made the necessary modifications in the devicetree.
This is the devicetree-section related to the displays:
tegra194-p3509-disp.dtsi (2.9 KB)

The full decompiled devicetree from the dtb file:
r35.dtsi (387.0 KB)

In /sys/kernel/debug/tegradc.*/out_type you can see that both displays are dp displays:

    DC OUTPUT:      TEGRA_DC_OUT_DP (3)


    DC OUTPUT:      TEGRA_DC_OUT_DP (3)

In pinmux config both hpd pins are configured identically.

Xorg conf shows that no displays were detected on that displayport.

Thanks for your help in advance!

#2

Did you check if your pinmux is correct?

#3

Yes, I did, both the config file and on the running system.
Here is the output for the pinmux for the hpd: (/sys/kernel/debug/pinctrl/2430000.pinmux/pinconfg-groups)

108 (dp_aux_ch0_hpd_pm0):
        pull=0
        tristate=1
        enable-input=1
        open-drain=0
        io-reset=0
        rcv-sel=0
        io-hv=0
        schmitt=0
        pull-down-strength=0
        pull-up-strength=0
        drive-type=0
        func=dp
        pad-power=0
109 (dp_aux_ch1_hpd_pm1):
        pull=0
        tristate=1
        enable-input=1
        open-drain=0
        io-reset=0
        rcv-sel=0
        io-hv=0
        schmitt=0
        pull-down-strength=0
        pull-up-strength=0
        drive-type=0
        func=dp
        pad-power=0

I checked the .xlsm file that generates the config files and the dp configs are correct there as well. (Both DP_AUX_CH0 and CH1 is configured):

image
image1796×88 6.09 KB

#4

Could you share your dmesg with monitor connected on the problematic port?

#5

Yes, this is the dmesg with only one monitor connected, to the non-working port, freshly booted:
dmesg.txt (74.4 KB)

#6

Hi,

Just to confirm, you are using 15210000 for this problematic display head right?

If so, then it could be pinmux or power sequence issue. How did you flash your pinmux setting?

[    7.450809] hpd: state 7 (Takeover from bootloader), hpd 0, pending_hpd_evt 1
[    7.460862] hpd: switching from state 7 (Takeover from bootloader) to state 0 (Reset)
[    7.468500] hpd: state 0 (Reset), hpd 0, pending_hpd_evt 0
[    7.474007] tegradc 15210000.display: blank - powerdown
[    7.474029] usb 2-3: new SuperSpeedPlus Gen 2 USB device number 2 using tegra-xusb
[    7.479071] extcon-disp-state external-connection:disp-state: cable 44 state 0 already set.
[    7.494806] Extcon DP: HPD disabled
[    7.498386] hpd: switching from state 0 (Reset) to state 1 (Check Plug)
[    7.505079] hpd: state 1 (Check Plug), hpd 0, pending_hpd_evt 0
[    7.510766] hpd: switching from state 1 (Check Plug) to state 3 (Disabled)
[    7.517830] tegra-se-nvhost 15810000.se: initialized
#7

No, 15210000 is the one unplugged. When I plug in the other display it displays correctly:

[  471.075327] tegradc 15210000.display: dp: plug event received
[  471.075452] hpd: state 3 (Disabled), hpd 1, pending_hpd_evt 1
[  471.075549] hpd: switching from state 3 (Disabled) to state 0 (Reset)
[  471.176409] hpd: state 0 (Reset), hpd 1, pending_hpd_evt 0
[  471.176509] tegradc 15210000.display: blank - powerdown
[  471.176643] extcon-disp-state external-connection:disp-state: cable 44 state 0 already set.
[  471.176653] Extcon DP: HPD disabled
[  471.176662] hpd: switching from state 0 (Reset) to state 1 (Check Plug)
[  471.176685] hpd: state 1 (Check Plug), hpd 1, pending_hpd_evt 0
[  471.176695] hpd: switching from state 1 (Check Plug) to state 2 (Check EDID)
[  471.180626] tegradc 15200000.display: blank - powerdown
[  471.180664] tegradc 15210000.display: blank - powerdown
[  471.184680] hpd: state 2 (Check EDID), hpd 1, pending_hpd_evt 0
[  471.190694] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  471.266720] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd
[  471.266951] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd
[  471.267177] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd
[  471.274242] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  471.284780] dp lt: state 0 (Reset), pending_lt_evt 1
[  471.284789] dp lt: switching from state 0 (Reset) to state 0 (Reset)
[  471.284797] dp lt: state 0 (Reset), pending_lt_evt 0
[  471.286267] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[  471.286277] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  471.286522] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[  471.286530] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[  471.286537] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[  471.286545] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[  471.286552] dp lt: tx_pu: 0x20
[  471.287506] dp lt: CR not done
[  471.287972] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  471.287977] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  471.287981] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  471.287985] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  471.287989] dp lt: CR retry
[  471.287993] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[  471.288001] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  471.288011] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  471.288018] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  471.288025] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  471.288031] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  471.288037] dp lt: tx_pu: 0x30
[  471.291079] dp lt: CR done
[  471.291087] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[  471.291096] dp lt: state 3 (channel equalization), pending_lt_evt 0
[  471.293634] dp lt: CE done
[  471.293641] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[  471.293947] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  471.294190] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.294429] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.294666] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.294903] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.295167] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.295411] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.295649] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.295886] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.296125] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.296383] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.296878] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.297124] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.297144] tegradc 15210000.display: blank - powerdown
[  471.327704] dp lt: state 5 (link training pass), pending_lt_evt 1
[  471.327709] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[  471.327714] dp lt: state 0 (Reset), pending_lt_evt 0
[  471.327721] dp lt: link training force disable
[  471.327725] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[  471.350827] tegra_nvdisp_handle_pd_disable: Powergated Head2 pd
[  471.351002] tegra_nvdisp_handle_pd_disable: Powergated Head1 pd
[  471.351913] tegra_nvdisp_handle_pd_disable: Powergated Head0 pd
[  471.352222] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  471.352235] tegradc 15210000.display: unblank
[  471.353699] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd
[  471.353882] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd
[  471.354101] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd
[  471.358808] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  471.368525] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[  471.368530] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[  471.368536] dp lt: state 0 (Reset), pending_lt_evt 0
[  471.369988] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[  471.369994] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  471.370231] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[  471.370237] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[  471.370243] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[  471.370268] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[  471.370274] dp lt: tx_pu: 0x20
[  471.371205] dp lt: CR done
[  471.371209] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[  471.371214] dp lt: state 3 (channel equalization), pending_lt_evt 0
[  471.373675] dp lt: CE done
[  471.373680] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[  471.374031] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  471.374338] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.374626] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.374867] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.375105] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.375346] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.375584] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.375843] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.376083] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.376369] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.376917] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.377246] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.377490] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.377497] tegradc 15210000.display: blank - powerdown
[  471.407364] dp lt: state 5 (link training pass), pending_lt_evt 1
[  471.407389] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[  471.407394] dp lt: state 0 (Reset), pending_lt_evt 0
[  471.407399] dp lt: link training force disable
[  471.407403] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[  471.431423] tegra_nvdisp_handle_pd_disable: Powergated Head2 pd
[  471.431597] tegra_nvdisp_handle_pd_disable: Powergated Head1 pd
[  471.432679] tegra_nvdisp_handle_pd_disable: Powergated Head0 pd
[  471.433048] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  471.433061] tegradc 15210000.display: unblank
[  471.434663] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd
[  471.435221] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd
[  471.435637] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd
[  471.441257] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  471.451765] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[  471.451771] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[  471.451778] dp lt: state 0 (Reset), pending_lt_evt 0
[  471.453314] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[  471.453326] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  471.453575] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[  471.453584] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[  471.453591] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[  471.453598] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[  471.453605] dp lt: tx_pu: 0x20
[  471.454570] dp lt: CR done
[  471.454576] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[  471.454584] dp lt: state 3 (channel equalization), pending_lt_evt 0
[  471.457492] dp lt: CE done
[  471.457501] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[  471.457734] extcon-disp-state external-connection:disp-state: cable 44 state 1
[  471.457745] Extcon DP: HPD enabled
[  471.457759] hpd: switching from state 2 (Check EDID) to state 4 (Enabled)
[  471.458955] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  471.459235] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.459505] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.459768] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.460031] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.460288] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.460806] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.461123] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.461388] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.461647] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.461911] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.462175] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.462708] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  471.464581] tegradc 15200000.display: blank - powerdown
[  471.464599] tegradc 15210000.display: blank - powerdown
[  471.491100] dp lt: state 5 (link training pass), pending_lt_evt 1
[  471.491106] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[  471.491129] dp lt: state 0 (Reset), pending_lt_evt 0
[  471.491139] dp lt: link training force disable
[  471.491142] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[  471.519996] tegra_nvdisp_handle_pd_disable: Powergated Head2 pd
[  471.520568] tegra_nvdisp_handle_pd_disable: Powergated Head1 pd
[  471.536739] tegra_nvdisp_handle_pd_disable: Powergated Head0 pd
[  471.594917] tegradc 15210000.display: blank - powerdown
[  471.595250] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  471.595304] tegradc 15210000.display: unblank
[  471.596929] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd
[  471.597673] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd
[  471.597913] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd
[  471.603766] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  471.613917] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[  471.613924] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[  471.613931] dp lt: state 0 (Reset), pending_lt_evt 0
[  471.615412] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[  471.615420] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  471.615664] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[  471.615672] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[  471.615679] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[  471.615686] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[  471.615692] dp lt: tx_pu: 0x20
[  471.616696] dp lt: CR done
[  471.616709] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[  471.616717] dp lt: state 3 (channel equalization), pending_lt_evt 0
[  471.619156] dp lt: CE done
[  471.619163] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[  471.619287] tegradc 15210000.display: unblank
[  471.619322] tegradc 15200000.display: blank - powerdown
[  472.036504] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  477.156485] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  482.276998] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  485.252932] start_addr=(0x20000), end_addr=(0x40000), buffer_size=(0x20000), smp_number_max=(16384)
[  487.396522] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  492.516632] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  497.636447] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  502.757032] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  507.877419] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  512.996819] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  518.117095] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  523.236707] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  528.356516] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  533.476536] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0
[  538.596506] snd_hda_codec_hdmi hdaudioC1D3: HDMI: Unknown ELD version 0

The one that doesn’t work seems to be 15200000.

#8

Ok, when you hotplut the cable to problematic port, did dmesg show anything new?

#9

No, nothing happens when I hotplug the not working displayport. No new dmesg messages.

#10

Then pinmux is still the one that should be checked… how did you update your pinmux?

#11

I generated the initial config using the xlsm file and used the python scripts to create the dtsi files for the pinmux then flashed the system with flash.sh.

#12

sorry, please directly share your exact steps. Such description won’t really help.

#13

I used the following steps to both compile the kernel and flash the system (as well as updating the pinmux):

NVIDIA kernel 5.10 guide
This is a guide for the Jetson linux verison 35.1

1. Download the packages needed to compile the system

These packages can be downloaded from here: https://developer.nvidia.com/embedded/jetson-linux
You will need:
	Driver Package (BSP)
	Sample Root Filesystem
	Driver Package (BSP) sources
	Bootlin Toolchain gcc 9.3


  $mkdir downloads
  $cd downloads
  Download the packages


	You will have the following files in the download folder:
		bootlin-toolchain-gcc-93 (if you get it with wget) or aarch64--glibc--stable-final.tar.gz
		jetson_linux_r35.1.0_aarch64.tbz2
		public_sources.tbz2
		tegra_linux_sample-root-filesystem_r35.1.0_aarch64.tbz2


2. Unpack the packages
	$cd ..
    	$tar -xjf downloads/jetson_linux_r35.1.0_aarch64.tbz2
 	$sudo tar -C Linux_for_Tegra/rootfs/ -xpf downloads/tegra_linux_sample-root-filesystem_r35.1.0_aarch64.tbz2
	$mkdir toolchain
	$tar -C toolchain/ -xf downloads/aarch64--glibc--stable-final.tar.gz
	$mkdir -p misc/public_sources
	$mkdir -p kernel/kernel_out
        $tar -C misc/public_sources/ -xf downloads/public_sources.tbz2


3. Apply the nvidia binaries to the rootfs
	$cd Linux_for_Tegra/
    	$sudo ./apply_binaries.sh
    	$cd ..

4.Download the kernel from the git
	$cd Linux_for_Tegra/
	$./source_sync.sh
	
When propted give this tag: jetson_35.1

5. Add the rtd sources to the kernel

(These sources are uploaded to the Hardware_Projects\NVidia_CPU\Software\Linux\kernel_510\rtd\)
	$cp rtd/tegra19x-mb1-pinmux-p3668-a01.cfg rtd/tegra19x-mb1-padvoltage-p3668-a01.cfg Linux_for_Tegra/bootloader/t186ref/BCT/
	$cp rtd/tegra194-fixed-regulator-p3668.dtsi rtd/tegra194-p3668-common.dtsi rtd/tegra194-p3509-disp.dtsi rtd/tegra194-super-module-e2614.dtsi Linux_for_Tegra/sources/hardware/nvidia/platform/t19x/jakku/kernel-dts/common/

6. Fix some github download order bugs, this is not needed if you extracted the kernel source from the downloaded files, this step is only needed for initial setup
	$cd Linux_for_Tegra/sources/kernel/nvidia/
	$git init
	$git remote add origin git://nv-tegra.nvidia.com/linux-nvidia.git
	$git fetch --depth=1 origin jetson_35.1
	$git checkout FETCH_HEAD


6. Building the kernel

	Copy the nvbuild.sh script from rtd folder:
	$cp rtd/nvbuild.sh Linux_for_Tegra/sources/
	$cp rtd/nvcommon_build.sh Linux_for_Tegra/sources/

	$export CROSS_COMPILE_AARCH64_PATH=$PWD/toolchain/
	$export CROSS_COMPILE_AARCH64=$PWD/toolchain/bin/aarch64-buildroot-linux-gnu-
	$cd Linux_for_Tegra/sources/

	$./nvbuild.sh 
	$./nvbuild.sh -o ../../kernel/kernel_out/

	Copy nvgpu driver:
	$sudo cp kernel/kernel_out/drivers/gpu/nvgpu/nvgpu.ko Linux_for_Tegra/rootfs/usr/lib/modules/5.10.104-tegra/kernel/drivers/gpu/nvgpu/nvgpu.ko

	Replace the device tree and kernel Image:
	$cp -rv kernel/kernel_out/arch/arm64/boot/Image Linux_for_Tegra/kernel/
	$cp -rv kernel/kernel_out/arch/arm64/boot/dts/nvidia/ Linux_for_Tegra/kernel/dtb/


7. Flash the built system:
	$cd Linux_for_Tegra
	$sudo ./flash.sh p3509-0000+p3668-0001-qspi-emmc mmcblk0p1

8. Reboot and configure the username, hostname.

This is the setup we have been using internally for the r35 version.

#14

@WayneWWW do you have an update on this?

#15

What content is in that cfg file?

#16

This is the pinmux .cfg file:
tegra19x-mb1-pinmux-p3668-a01.cfg (27.2 KB)

#17

@WayneWWW

Is there a way to verify the correct pinmux is running from the running system?

We have a running (and working) system with the previous big release (with kernel 4.x.x, I think R32). We are using the same pinmux, same setup as this system. As far as I can tell the way to modify the pinmux didn’t change between these two releases.

#18

You could directly use register dump and compare the result from registers between these two release in kernel.

Search “devmem2” or “devmem” tool from ubuntu. And you could check the cfg file for the register address.

If pinmux is same, then we may need check the dpaux state/register.