We are unable to display from the DP port on the NX SDK Reference Carrier board. Are there modifications need to the kernel or DTS?
Regards,
J
I am able to use DP monitor with NX devkit, so :
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It may be related to your monitor. You may try booting with a HDMI monitor or none and plug DP one minute later. See if it changes and check kernel messages.
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However, in my case booting with DP display only seems to have some times blanking and issuing many kernel messages such as:
[ 8.436841] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
[ 8.437088] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 8.437336] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 8.437583] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 8.437830] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 8.438077] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 8.438323] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 8.438570] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 8.438816] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 8.439063] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 8.439327] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 8.439575] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 8.439823] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
...
[ 8.445790] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10420000 did not specify bpp
[ 8.445819] tegradc 15210000.nvdisplay: blank - powerdown
[ 8.480221] dp lt: state 5 (link training pass), pending_lt_evt 1
[ 8.480244] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[ 8.480248] dp lt: state 0 (Reset), pending_lt_evt 0
[ 8.480254] dp lt: link training force disable
[ 8.480257] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[ 8.501221] extcon-disp-state external-connection:disp-state: cable 46 state 0
[ 8.501224] Extcon AUX0(DP) disable
[ 8.501226] dp_audio switch 0
[ 8.503664] tegra_nvdisp_handle_pd_disable: Powergated Head2 pd
[ 8.503762] tegra_nvdisp_handle_pd_disable: Powergated Head1 pd
[ 8.504399] tegra_nvdisp_handle_pd_disable: Powergated Head0 pd
[ 8.504734] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
[ 8.504746] tegradc 15210000.nvdisplay: unblank
[ 8.505434] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd
[ 8.505542] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd
[ 8.505648] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd
[ 8.507381] Parent Clock set for DC pll_d
[ 8.511536] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
[ 8.521066] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[ 8.521070] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[ 8.521076] dp lt: state 0 (Reset), pending_lt_evt 0
[ 8.522702] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[ 8.522710] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 8.522964] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 8.522976] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 8.522986] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 8.522996] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 8.523003] dp lt: tx_pu: 0x20
[ 8.523952] dp lt: CR not done
[ 8.524419] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 8.524422] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 8.524424] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 8.524426] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 8.524428] dp lt: CR retry
[ 8.524431] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 8.524436] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 8.524448] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 8.524458] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 8.524467] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 8.524477] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 8.524483] dp lt: tx_pu: 0x30
[ 8.525427] dp lt: CR not done
or
[ 10.352263] Extcon DP: HPD enabled
[ 10.352291] hpd: Display connected, hpd_switch 1
[ 10.352295] hpd: switching from state 2 (Check EDID) to state 4 (Enabled)
[ 10.352305] hpd: state 4 (Enabled), hpd 1, pending_hpd_evt 1
[ 10.352307] hpd: No EDID change. No userspace active. Using cached mode to initialize dc!
[ 10.352310] hpd: switching from state 4 (Enabled) to state 2 (Check EDID)
[ 10.352337] hpd: state 2 (Check EDID), hpd 1, pending_hpd_evt 0
[ 10.393908] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
[ 10.394149] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 10.394387] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 10.394640] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 10.394890] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 10.395143] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
....
[ 10.402735] tegradc 15210000.nvdisplay: blank - powerdown
[ 10.426720] Root device found: mmcblk0p1
[ 10.428032] Found dev node: /dev/mmcblk0p1
[ 10.448937] dp lt: state 5 (link training pass), pending_lt_evt 1
[ 10.448941] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[ 10.448946] dp lt: state 0 (Reset), pending_lt_evt 0
[ 10.448953] dp lt: link training force disable
[ 10.448955] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
and finally working :
[ 38.469220] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10420000 did not specify bpp
[ 38.551958] tegradc 15210000.nvdisplay: blank - powerdown
[ 38.552239] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
[ 38.552292] tegradc 15210000.nvdisplay: unblank
[ 38.553183] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd
[ 38.553312] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd
[ 38.553429] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd
[ 38.555402] Parent Clock set for DC pll_d
[ 38.559697] tegradc 15210000.nvdisplay: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
[ 38.569053] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[ 38.569059] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[ 38.576007] dp lt: state 0 (Reset), pending_lt_evt 0
[ 38.577623] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[ 38.577632] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 38.577878] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 38.577888] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 38.577897] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 38.577906] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 38.577913] dp lt: tx_pu: 0x20
[ 38.578858] dp lt: CR not done
[ 38.579360] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 38.579363] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 38.579366] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 38.579369] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 38.579371] dp lt: CR retry
[ 38.579375] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 38.579381] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 38.579395] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 38.579404] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 38.579413] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 38.579422] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 38.579427] dp lt: tx_pu: 0x30
[ 38.580415] dp lt: CR not done
[ 38.580890] dp lt: new config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 38.580893] dp lt: new config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 38.580896] dp lt: new config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 38.580899] dp lt: new config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 38.580901] dp lt: CR retry
[ 38.580905] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 38.580911] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 38.580924] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 38.580933] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 38.580942] dp lt: config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 38.580952] dp lt: config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 38.580957] dp lt: tx_pu: 0x40
[ 38.581912] dp lt: CR done
[ 38.581916] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[ 38.581922] dp lt: state 3 (channel equalization), pending_lt_evt 0
[ 38.583395] dp lt: CE not done
[ 38.583872] dp lt: new config: lane 0: vs level: 2, pe level: 1, pc2 level: 0
[ 38.583875] dp lt: new config: lane 1: vs level: 2, pe level: 1, pc2 level: 0
[ 38.583878] dp lt: new config: lane 2: vs level: 2, pe level: 1, pc2 level: 0
[ 38.583881] dp lt: new config: lane 3: vs level: 2, pe level: 1, pc2 level: 0
[ 38.583891] dp lt: config: lane 0: vs level: 2, pe level: 1, pc2 level: 0
[ 38.583901] dp lt: config: lane 1: vs level: 2, pe level: 1, pc2 level: 0
[ 38.583910] dp lt: config: lane 2: vs level: 2, pe level: 1, pc2 level: 0
[ 38.583920] dp lt: config: lane 3: vs level: 2, pe level: 1, pc2 level: 0
[ 38.583925] dp lt: tx_pu: 0x60
[ 38.584193] dp lt: CE retry
[ 38.584197] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization)
[ 38.584202] dp lt: state 3 (channel equalization), pending_lt_evt 0
[ 38.585430] dp lt: CE not done
[ 38.585907] dp lt: new config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 38.585910] dp lt: new config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 38.585913] dp lt: new config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 38.585916] dp lt: new config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 38.585925] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 38.585935] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 38.585944] dp lt: config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 38.585954] dp lt: config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 38.585960] dp lt: tx_pu: 0x40
[ 38.586228] dp lt: CE retry
[ 38.586232] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization)
[ 38.586237] dp lt: state 3 (channel equalization), pending_lt_evt 0
[ 38.588372] dp lt: CE done
[ 38.588376] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[ 38.588544] extcon-disp-state external-connection:disp-state: cable 46 state 1
[ 38.588549] Extcon AUX0(DP): enable
[ 38.588553] dp_audio switch 1
[ 38.588636] tegradc 15210000.nvdisplay: unblank
[ 38.588653] tegradc 15200000.nvdisplay: blank - powerdown
[ 42.534777] fuse init (API version 7.26)
[ 42.784809] tegradc 15210000.nvdisplay: unblank
[ 42.784824] tegradc 15200000.nvdisplay: blank - powerdown
Also, with the same monitor, the DP image is like somewhat excessively bright or bleached as compared to HDMI (confirmed using side by side PIP mode). This monitor only allows contrast adjustment per input which didn’t help.
I haven’t tried another DP cable because I only have one, but this one is supposed to support 8K, so I guess it should be ok.
I do see different EDIDs for both HDMI and DP displays, although here they are just halfs of same monitor in PIP mode:
edid0.txt (784 Bytes) edid1.txt (784 Bytes)
Not sure if the issue is in my monitor or Jetson NX.
Does anyone knows if there is a way to tune brightness of DP output ?
Thanks, Honey. Just to be clear, are you using a DP cable to DP monitor, without any DP-to-HDMI conversion anywhere? We’ve tried about everything, but I’ll try a DP cable and DP monitor and wait a while until after Linux boots, and get back to you.
I’ve also tried DP-to-HDMI adapter to HDMI monitor, but not sure it’s an active adapter, have a couple of more coming tomorrow.
Regards,
J
Yes. I’m using a UW monitor with 1 DP input and 2 HDMI inputs, so I used a DP to DP cable and a HDMI to HDMI cable.
Try avoiding converters as much as possible, some might raise issues on Jetsons with display controler and X server.
Great, thanks. We have the same. Will try it with delay. Much thanks and regards, J
DisplayPort to DP monitor with DP cable worked fine, with and without additional HDMI monitor hooked up. Thanks!