Enable UART3 (THS3) on R32

Following Nvidia documentation:

To enable ttyTHS3 (UART3) we should edit :

gpio@2200000 {
                wifi_over_pcie {
                        gpios = <TEGRA_MAIN_GPIO(R, 4) 0>;
                        label = "wifi-over-pcie";
                        status = "disabled";


gpio@2200000 {
                wifi_over_pcie {
                        gpios = <TEGRA_MAIN_GPIO(R, 4) 0>;
                        label = "wifi-over-pcie";
                        status = "okay";

(see base info here : https://devtalk.nvidia.com/default/topic/1062388/how-to-change-the-selection-of-the-uart3-module-pin-h9-h10-/ )

But recompiling the kernel, and re flashing the dtb leads to an un-bootable image.

Also Nvidia documentation has 5 UART (4 + debug (ttyS0) ):

From Nvidia documentation v1.2
        (p.7) table define UART as x5  
        (p.40) UART[7,3:0], that we read as port 7 & 0 to 3 included  (i.e. 4 ports + 1 -> 5 ports).

update kernel is now boot-able, but THS3 is still not working.

Did we miss any step?

Please check tips in

So from https://devtalk.nvidia.com/default/topic/1030758/jetson-tx2/uart3-not-able-to-receive-data/post/5243967/#5243967 we are not aware that we should remove the PIO mode from the RX of THS3.

ubuntu@tx2:~$ dmesg | grep 3130000
[    0.431436] iommu: Adding device 3130000.serial to group 17
[    1.123346] serial-tegra 3130000.serial: RX in PIO mode
[    1.124400] 3130000.serial: ttyTHS3 at MMIO 0x3130000 (irq = 39, base_baud = 0) is a TEGRA_UART

We haven’t find how to disable the PIO mode, and not found any @3130000 anywhere in the kernel code.
EDIT: also Tx isn’t working too.

Is there any documentation on that part ?

Also we didn’t found anything yet on UART4.

We have verified it working with getty. Please check

Please try to put rx in “dma-names” under the device tree of serial@3130000 to disable RX PIO mode.


Thank you for those, we will recompile for THS3 & let you know.

In the mean time can you give us some leads on the UART4 mentioned in the documentation ?

Hi Elleryn,

I don’t get your point of “UART4 mentioned in the document”. What document are you referring to?

Jetson tx2 pins mapping to tegra function as below list

UART0 -> UART1 debug
UART1 -> UART3 serial port
UART2 -> UART2 m.2 socket
UART3 -> UART4 Misc (mux between on-module WLAN/BT)
UART7 -> UART7 Misc

You are trying to use UART4 as THS3, aren’t you?


We currently have ttySO (debug), ttyTHS1, ttyTHS2 and hopefully ttyTHS3 after trying your previous post (I’m currently out of the office, so will report to you on Wednesday).

Yes I should have referenced UART7 not uart4.

Is there any specific kernel modification to enable it? Also which tty should we open?

You may need to set UART7 status to enabled in device tree.

Just to let you know.

We are going to test this as soon as possible, but our developers have nearly all their time taken by the CES 2020.

We will come back to you when we will test those points.

Thank you for your help.