Enabling SPI and setting pinmux on JetPack 4.2.2 (L4T 32.2 and higher) not working

I’m trying to enable SPI1 on header J41. I tried few different topics to get this done, but none of them seems to solve the problem.
Here is my DT:

gpio@6000d000 {
    spi1_pins: spi1 {
        gpio-hog;
	function;
        gpios = <
            TEGRA_GPIO(C, 0) 0 
            TEGRA_GPIO(C, 1) 0 
            TEGRA_GPIO(C, 2) 0 
            TEGRA_GPIO(C, 3) 0 
            TEGRA_GPIO(C, 4) 0
            >;
            label = "SPI1_MOSI", "SPI1_MISO", "SPI1_SCK", 
               "SPI1_CS0", "SPI1_CS1";
            line-name = "spi1-line";
            };

spi@7000d400 {
    status = "okay";
	spidev {
	    #address-cells = <1>;
            #size-cells = <0>;
            compatible = "spidev";
            reg = <0>;
            spi-max-frequency = <500000>;
            //controller-data {
            nvidia,enable-hw-based-cs;
            nvidia,cs-setup-clk-count = <0x1e>;
            nvidia,cs-hold-clk-count = <0x1e>;
            nvidia,rx-clk-tap-delay = <0x1f>;
            nvidia,tx-clk-tap-delay = <0x0>;
            //};
    };
};

According to this topic:
https://devtalk.nvidia.com/default/topic/1050427/jetson-nano/enabling-spidev-on-the-jetson-nano-is-hanging-when-flashing/
and this dts:
https://github.com/rt-net/JetsonNano_DT_SPI
everything is seems to be done right, but looking at GPIO settings it looks like it’s not set:

~$: sudo cat /sys/kernel/debug/tegra_gpio
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 A: 0:0 64 40 40 24 00 00 000000
 B: 0:1 f0 00 00 00 00 00 000000
 C: 0:2 1f 00 00 00 00 00 000000
 D: 0:3 00 00 00 00 00 00 000000
 E: 1:0 40 00 00 00 00 00 000000
 F: 1:1 00 00 00 00 00 00 000000
 G: 1:2 0c 00 00 04 00 00 000000
 H: 1:3 fd 99 00 60 00 00 000000
 I: 2:0 07 07 02 00 00 00 000000
 J: 2:1 f0 00 00 00 00 00 000000
 K: 2:2 00 00 00 00 00 00 000000
 L: 2:3 00 00 00 00 00 00 000000
 M: 3:0 00 00 00 00 00 00 000000
 N: 3:1 00 00 00 00 00 00 000000
 O: 3:2 00 00 00 00 00 00 000000
 P: 3:3 00 00 00 00 00 00 000000
 Q: 4:0 00 00 00 00 00 00 000000
 R: 4:1 00 00 00 00 00 00 000000
 S: 4:2 a0 80 00 00 00 00 000000
 T: 4:3 01 01 00 00 00 00 000000
 U: 5:0 00 00 00 00 00 00 000000
 V: 5:1 03 00 00 02 00 00 000000
 W: 5:2 00 00 00 00 00 00 000000
 X: 5:3 78 08 08 30 00 60 606000
 Y: 6:0 06 00 00 02 00 00 000000
 Z: 6:1 0f 08 08 04 00 06 020600
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 01 00 00 00 00 00 000000
CC: 7:0 92 80 80 10 00 12 121200
DD: 7:1 01 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000

Is there any change for setting pinmux in kernel? Or this should be done now in different way (cboot?)

Try this…
https://devtalk.nvidia.com/default/topic/1062646/jetson-nano/updated-instructions-for-spi-on-nano-developmentkit-with-l4t-32-2-1/

@pawel.zabielowicz
For the GPIO problem have apply the change from below link

https://devtalk.nvidia.com/default/topic/1050427/jetson-nano/enabling-spidev-on-the-jetson-nano-is-hanging-when-flashing/post/5381403/#5381403