Hello everybody,
I run this command v4l2-ctl -d /dev/video1 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=3
and I can capture 3 frames, but got this messages
[ 94.149738] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 94.156239] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 94.369850] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 94.376361] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
I run this command v4l2-ctl -d /dev/video1 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=3 --set-ctrl low_latency_mode=1
and enable low_latency mode I can’t capture any frames and got this messages:
[ 297.412471] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 297.616426] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 297.824389] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 298.032411] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 298.036828] tegra-vi4 15700000.vi: ATOMP_FE syncpt timeout! err = -11
[ 298.248375] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 298.456349] tegra-vi4 15700000.vi: ATOMP_FE syncpt timeout! err = -11
[ 298.664336] tegra-vi4 15700000.vi: ATOMP_FE syncpt timeout!
[ 298.670029] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 298.680252] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x00000001
[ 298.688387] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x00000001
[ 298.748609] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x00000089
[ 298.756757] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x00000089
How can enable low_latency mode and capture without this messages?
I changed chan->timeout = msecs_to_jiffies(200);
to chan->timeout = msecs_to_jiffies(1000);
in vi4_fops.c and I can capture video, But the following messages are still displayed.
[ 94.149738] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 94.156239] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 94.369850] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 94.376361] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
How to solve this problem?
Hi @royayeazadi
These messages are showing there are some problems with the image or that the device-tree does not match what the camera is sending.
Is this a custom camera driver?
Are you using a custom board?
What type of camera is it (CSI, USB, other)?
Embedded SW Engineer at RidgeRun
Contact us: support@ridgerun.com
Developers wiki: https://developer.ridgerun.com/
Website: www.ridgerun.com
Hi jafeth.garcia
Thanks for your reply,
yes, this is custom camera driver.
yes, we are using a custom board.
the type of camera is CSI.
@royayeazadi
The issue could be related to the properties in the device-tree. You could try what is suggested here . Check these properties in device-tree:
active_w: should match sensor resolution width
active_h: should match sensor resolution height
line_length: Usually is equal to or greater value than resolution width.
Thanks your reply,
We checked these properties, These properties are set correctly.
@royayeazadi are the frames you captured showing a good image, no errors in the image itself?
You can save the RAW image:
v4l2-ctl -d /dev/video1 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=1 --stream-to=image.raw
You can check it with a program like vooya which can open RAW files
Hi jafeth.garcia
Thanks for reply,
I saved a RAW image with this, and check with “https://rawpixels.net/ ”. The image is good.
Hi royayeazadi,
Which is the value of your pixel_clk_hz ?
Please check if it is adjusted to the guide that is attached below.
https://docs.nvidia.com/jetson/archives/r35.1/DeveloperGuide/text/SD/CameraDevelopment/SensorSoftwareDriverProgramming.html#sensor-pixel-clock
If it the pixel_clk_hz follows this guide, try to boost it. That could work.
Best,
JDiego Delgado
Embedded SW Engineer at RidgeRun
Contact us: support@ridgerun.com
Developers wiki: https://developer.ridgerun.c om/
Website: www.ridgerun.com
system
Closed
March 24, 2023, 4:29pm
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