PXL_SOF error on system load

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

Hi,

we have a camera driver which works great most of the time but if we add some specific load (encoding / cuda processing) to the tx2, some PXL_SOF error appears frequently every 3-5 Minutes:

[Jun12 08:06] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[  +0.003990] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[  +0.000003] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[  +0.007995] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[  +0.000002] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[  +0.026015] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[  +0.054009] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) INTR_STATUS 0x00000004
[  +0.007839] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) ERR_INTR_STATUS 0x00000004
[  +0.008181] nvcsi 150c0000.nvcsi: csi4_cil_check_status (2) CIL_INTR_STATUS 0x00000044
[  +0.007925] nvcsi 150c0000.nvcsi: csi4_cil_check_status (2) CIL_ERR_INTR_STATUS 0x00000044
[  +0.032052] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CIL_INTR_STATUS 0x00000024
[  +0.008025] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CIL_ERR_INTR_STATUS 0x00000024
[  +0.052013] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) INTR_STATUS 0x00000004
[  +0.007863] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERR_INTR_STATUS 0x00000004
[  +0.008185] nvcsi 150c0000.nvcsi: csi4_cil_check_status (4) CIL_INTR_STATUS 0x00000044
[  +0.007932] nvcsi 150c0000.nvcsi: csi4_cil_check_status (4) CIL_ERR_INTR_STATUS 0x00000044
[  +9.279933] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[  +0.006391] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[  +0.009617] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[  +0.006396] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[  +0.049608] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CIL_INTR_STATUS 0x00000064
[  +0.008009] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CIL_ERR_INTR_STATUS 0x00000064
[  +0.051983] nvcsi 150c0000.nvcsi: csi4_cil_check_status (0) CIL_INTR_STATUS 0x00000044
[  +0.007937] nvcsi 150c0000.nvcsi: csi4_cil_check_status (0) CIL_ERR_INTR_STATUS 0x00000044

Any idea where this comes from and how to further debug this?

2

hello crossfire5,

  1. may I know which JetPack release you’re working with.
  2. may I know what’s the process you added for execution, please share it for reference.
  3. BTW, you could also check the [Tegra X2 (Parker Series SoC) Technical Reference Manual] for the register reporting.
    for example,
    please check the NVCSI_STREAM_0_INTR_STATUS_0 register description.
NVCSI_STREAM_0_INTR_STATUS_0 = 0x44 
bit 2: intr_stat_pd_crc_err_vc0
bit 6: intr_stat_pd_crc_err_vc1

please have a try to ignore the CRC errors, you might refer to Topic 1037609 for the patches.
thanks

3

Hi Jerry,

  1. We are on L4T 28.2.1
  2. Its a custom software for stitching 6 cameras. it uses v4l2 for grabbing, cuda for stitching and gstreamer with omxh265enc for encoding. We are passing managed memory to v4l2 in userptr mode to be able to directly access the frames with cuda.
    3)Thank you I will try to ignore crc errors, I will share the results
4

Hi crossfire5! Did you manage to figure this out? I am having a very similar issue (only when encoding), and I’m wondering what might be causing this. Did ignoring CRC errors fix the issue for you?