TX2 video input, suggestions for debugging PXL_SOF syncpt timeout?

We’re putting together a TX2 based board with video capture hardware that feeds
into a CSI converter and into the CSI inputs on the TX2. Thanks in part to
the information from this forum, we’ve made good progress.

We’re to the point where we can configure the a/ds and converters on the board,
and there’s a camera driver in place modeled on the ov5693 example.

Our hardware guy has verified that video is being fed to the CSI converter
and data and clock are being routed to the TX2 CSI0 input.

I added the necessary video formats to the existing drivers, and added the
device tree entries per the camera developers guide part of the L4T
documentation, and a lot of things are working. The modules get loaded, the
media control linkages SEEM in place, and the v4l2 video device and subdevies
are created in /sys/devices and under /dev.

v4l2-ctl can see the device and shows the right values.

However, when I use v4l2-ctl to try and grab a frame, I get PXL_SOF syncpt timeout.

I’ve enabled debug in the nvcsi control code, and it looks as if it’s being started.

Here’s what media-ctl -p shows:

Media controller API version 0.1.0

Media device information
driver          tegra-vi4
model           NVIDIA Tegra Video Input Device
bus info        
hw revision     0x3
driver version  0.0.0

Device topology
- entity 1: 150c0000.nvcsi-1 (2 pads, 2 links)
            type V4L2 subdev subtype Unknown flags 0
            device node name /dev/v4l-subdev0
        pad0: Sink
                <- "cti_scout_sd_in 2-0001":0 [ENABLED]
        pad1: Source
                -> "vi-output, cti_scout_sd_in 2-00":0 [ENABLED]

- entity 2: cti_scout_sd_in 2-0001 (1 pad, 1 link)
            type V4L2 subdev subtype Sensor flags 0
            device node name /dev/v4l-subdev1
        pad0: Source
                [fmt:UYVY/640x480 field:none]
                -> "150c0000.nvcsi-1":0 [ENABLED]

- entity 3: vi-output, cti_scout_sd_in 2-00 (1 pad, 1 link)
            type Node subtype V4L flags 0
            device node name /dev/video0
        pad0: Sink
                <- "150c0000.nvcsi-1":1 [ENABLED]

And what attempting a frame grab shows

# v4l2-ctl -d /dev/video0 --stream-mmap --stream-count=1 --stream-to=test.raw
[[ 5756.987117] nvcsi 150c0000.nvcsi: csi port:1
[ 5756.991611] nvcsi 150c0000.nvcsi: csi4_start_streaming ports index=1, lanes=2
[ 5756.998778] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 5757.003606] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 5757.008598] nvcsi 150c0000.nvcsi: csi4_stream_config (1) read VC0_DPCM_CTRL = 00000000
[ 5757.016542] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 5757.021268] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 5757.027051] cti_scout_sd_in 2-0001: sim_sd_in_s_stream++
[ 5758.030426] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 5759.034435] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 5760.038439] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
<[ 5761.042433] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 5762.046443] tegra-vi4 15700000.vi: ATOMP_FE syncpt timeout!
[ 5762.052471] cti_scout_sd_in 2-0001: sim_sd_in_s_stream++
[ 5762.058816] nvcsi 150c0000.nvcsi: csi4_stop_streaming ports index=0, lanes=2
[ 5762.066029] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 5762.070804] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000200
[ 5762.076660] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 5762.082259] nvcsi 150c0000.nvcsi: csi4_cil_check_status 278


I’m looking for any insight about how to go forward debugging this.

Do I have the correct device tree entries so the camera common will
connect the proper CSI ports, i.e. is the media-ctl output correct?

What stream configuration parameters can be set for the csi input on
the tx2, or must be configured in the external CSI converters, to make
the link work rather than time out?

Are there any other problems people have run into that have caused the
PXL_SOF timeouts?

Any other ideas?



Make sure the output signal is MIPI compliance then try below comment.

I tried adjusting the value for DEFAULT_THS_SETTLE as described, but the symptom is still the same,
PXL_SOF syncpt timeout.

We are using a Toshiba TC348746 Parallel to CSI converter to convert Parallel YUY422 8-bit
sd data into CSI.

As I said, the hardware designer has checked and is pretty sure the signals are routed
properly, so the current conclusion is that’s it’s a configuration mismatch of some sort
between the parallel-to-csi converter and the csi input on the tx2.

Has anyone else run into similar problems? If so, how did you go
about debugging, and what did you find solved the problems?


We have made changes to the CSI translator and now abut half the time we try
to do a v4l2-ctl based capture we get the following errors:

[  633.260858] tegra-vi4 15700000.vi: Status:  4 channel:00 frame:0000
[  633.267130] tegra-vi4 15700000.vi:          timestamp sof 642907318592 eof 642907327520 data 0x00000200
[  633.276517] tegra-vi4 15700000.vi:          capture_id 126 stream  0 vchan  0
VIDIOC_DQBUF: failed: Input/output error

As near as I can tell, this is a VI_CAPTURE_STATUS_CHANSEL_FAULT from the rt-cpu that’s
transferring data from the CSI input to the VI subsystem.

Is there any way I can debug this further to get an idea of what the problem is?

Thanks in advance,


Discussed at https://devtalk.nvidia.com/default/topic/1025921/understanding-vi-error-messages-/