Fix interrupts declarations for GICv3

discovered there is a problem with running all hypervisors on NVIDIA Orin that’re trying to utilize the GICv3 features.
This includes qemu with GICv3 enabled and all RustVMM-based hypervisors – they fail with “failed to create IRQ chip: No such device (os error 19)” diagnostics.
Investigation discovered that necessary control structures for GICv3 are not created during kernel device initialization in the kvm subsystem. That leads to bug in the DTS – incomplete interrupts declaration in interrupt-controller section.
Fixed by adding the necessary declarations.

	diff a/tegra234-soc-minimal.dtsi b/tegra234-soc-minimal.dtsi 
45a46,48
		reg = <0x0 0x0f400000 0x0 0x00010000    /* GICD */
		       0x0 0x0f440000 0x0 0x00200000>;  /* GICR CPU 0-15 */
		ranges;
>               interrupts = <GIC_PPI 9
>                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>               interrupt-parent = <&intc>;

	         status = "disabled";

		gic_v2m: v2m@f410000 {

Hi,
Thanks for the sharing. We will check the patch with our teams.

Thank you for accepting the patch, would be great if you can share a response/result back!

Yes, the change is right. Have added to our tree.
Thank you for suggesting it.