I am working on a project where FPGA has PCIe endpoint connected to PCIe Root of TX1 and act as bus master meaning that the FPGA can initiate data transfer upstream to TX1. I configured my FPGA AXI_to_PCIe BAR for some random memory address (0x2000_0000) but the truth is that, being an FPGA guy, I have no idea how and where to map the PCIe BAR address. Do I need to reserve an address space for thisand just hard-code it into the FPGA PCIe? We need to DMA-copy data from FPGA to TX1 memory for GPU to be able to do some processing with it later. Can you please advice?
I am able to lspci and correctly configure the FPGA PCIe endpoint to be bus master and enable it.
Thank you in advance for your time.