Generate MCLK on Jetson Orin NX

Robotics & Edge Computing Jetson Systems Jetson Orin NX
1

I want to generate MCLK: 24MHz clock for 2D ToF camera irs2381c from the Nvidia Jetson Orin NX.
I have added the relevant GPIO as output in pinmux file:

				// TOF MCLK (pin 122)
				spi5_mosi_pac2 {
					nvidia,pins = "spi5_mosi_pac2";
					nvidia,function = "extperiph1";
					nvidia,pin-label = "spi5_mosi_pac2";
					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
					nvidia,tristate = <TEGRA_PIN_DISABLE>;
					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				};

And added the camera in the device tree overlay:


						irs2381c_cam1: irs2381c@3d {
							compatible = "infineon,irs2381c";
							/* I2C device address */
							reg = <0x3d>;  //(0x7a(W)/0x7b(R)>>1)

							/* V4L2 device node location */
							devnode = "video3";
							/* MCLK */
							clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
									<&bpmp TEGRA234_CLK_EXTPERIPH1>;
							clock-names = "extperiph1", "pllp_grtba";
							assigned-clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>;
							assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
							assigned-clock-rates = <24000000>;
							mclk = "extperiph1";
							// Reset is inverted on the board by the transistor
							reset-gpios = <&gpio CAM_2DTOF_PWDN GPIO_ACTIVE_HIGH>;  // Pin 120, active low PWDN

							sensor_model = "irs2381c";
							use_sensor_mode_id = "true";

However, the MCLK is not present when I check with logic analyzer.
I get this output from the driver:

$ sudo dmesg | grep irs2381
[ 40.622598] irs2381c 13-003d: avdd, iovdd and/or dvdd reglrs. not present, assume sensor powered independently
[ 40.622855] irs2381c 13-003d: tegracam sensor driver:irs2381c_v2.0.6
[ 40.623022] irs2381c 13-003d: irs2381c_power_on: skip_power_seqn: reset-gpio 486: set value 0
[ 40.623025] irs2381c 13-003d: now the sensor should respond
[ 40.833698] irs2381c 13-003d: Failed to read chip ID
[ 40.833706] irs2381c 13-003d: irs2381c_power_off: reset-gpio 486: set value 1
[ 40.838749] irs2381c 13-003d: Failed to read chip ID, power off, fallback, try with iverted polarity:
[ 41.039587] irs2381c 13-003d: Failed to read chip ID in a fallback attempt
[ 41.039596] irs2381c 13-003d: Read unknown chip ID 0x0000 in a fallback attempt
[ 41.039665] irs2381c 13-003d: board setup failed
[ 41.039720] irs2381c: probe of 13-003d failed with error -121

Full files:
tegra234-diamond-orb.dts.txt (38.3 KB)
tegra234-p3768-0000-diamond-pinmux.dtsi.txt (2.6 KB)

dmesg-mclk-irs2381-tof.txt (69.7 KB)

What do I need to do to generate the output clock from Jetson on pin 122 “spi5_mosi_pac2”?

2

*** Please note that this reply is generated by LLM automatically ***

To generate the MCLK 24MHz clock for the 2D ToF camera irs2381c from the Nvidia Jetson Orin NX, you have already taken the correct steps by adding the relevant GPIO as output in the pinmux file and adding the camera in the device tree overlay. However, since the MCLK is not present when checked with a logic analyzer, there are a few potential issues to investigate:

  1. Pin Configuration: Double-check that the pin configuration in the pinmux file is correct. Ensure that the pin 122 (spi5_mosi_ac2) is configured as an output and is not being used by any other peripheral.
  2. Device Tree Overlay: Verify that the device tree overlay is correctly configured to enable the MCLK output on pin 122. Check the tegra234-diamond-orb.dts file and the tegra234-p3768-0000-diamond-pinmux.dtsi file to ensure that the pin is correctly configured.
  3. Clock Configuration: The MCLK clock is typically generated by the PLL (Phase-Locked Loop) or the clock controller. Check the clock configuration in the device tree overlay to ensure that the MCLK clock is enabled and set to the correct frequency (24MHz).
  4. GPIO Configuration: Although you mentioned that the GPIO is configured as an output, double-check that the GPIO is not being used by any other peripheral or driver. You can use the gpio command-line tool to verify the GPIO configuration.
  5. Driver Configuration: Check the driver configuration for the camera (irs2381c) to ensure that it is correctly configured to use the MCLK clock. You can check the driver source code or the kernel logs to see if there are any errors or warnings related to the MCLK clock.
  6. Clock Routing: On some SoCs, clocks need to be routed through specific clock controllers or muxes. Check the Jetson Orin NX documentation to see if there are any specific clock routing requirements for the MCLK clock.
  7. Hardware Issues: Although unlikely, there could be a hardware issue with the pin or the clock circuitry. If you have access to the hardware design files or schematics, verify that the pin is correctly connected to the clock circuitry.

To troubleshoot the issue, you can try the following:

  • Use the gpio command-line tool to verify the GPIO configuration and try setting the pin as an output manually.
  • Use the clk command-line tool to verify the clock configuration and try setting the MCLK clock frequency manually.
  • Check the kernel logs for any errors or warnings related to the MCLK clock or the camera driver.
  • Use a logic analyzer to verify that the MCLK clock is not present on any other pins.

If none of these steps resolve the issue, it may be helpful to provide more information about the device tree overlay, pinmux file, and driver configuration to further assist in troubleshooting the problem.

*** Please give the thumbs up if you get answers you like. Or provide feedback to help us improve the answer. ***

4
  • Use the gpio command-line tool to verify the GPIO configuration and try setting the pin as an output manually.
  • Use the clk command-line tool to verify the clock configuration and try setting the MCLK clock frequency manually.

There is no gpio or clk command-line tools.
For GPIO, I can use gpiod/gpioset, but what about clock? I searched and didn’t find any CLI tool to control clocks on Nvidia Jetson.

5

I don’t think think pin can use by clock output.

Why not use CAM1_MCLK?

image
image1766×1779 244 KB

6

I was able to make it work on Orin NX by using extperiph2 clock, like this:

		irs2975c_cam1: irs2975c@3d {
							compatible = "infineon,irs2975c";
							/* I2C device address */
							reg = <0x3d>;  //(0x7a(W)/0x7b(R)>>1)

							/* V4L2 device node location */
							devnode = "video3";
							/* MCLK */
							clocks = <&bpmp TEGRA234_CLK_EXTPERIPH2>,
								<&bpmp TEGRA234_CLK_EXTPERIPH2>;
							clock-names = "extperiph2", "pllp_grtba";
							assigned-clocks = <&bpmp TEGRA234_CLK_EXTPERIPH2>;
							assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
							assigned-clock-rates = <24000000>;
							mclk = "extperiph2";

Kudos to fouge (Cyril Fougeray) · GitHub for help and his eagle eye!