Hardware PWM update with Jetson.GPIO

Robotics & Edge Computing Jetson & Embedded Systems Jetson Nano
1

hello NVIDIA and everyone.

I found this update about hardware PWM support ! That’s great.

11. PWM
See samples/simple_pwm.py for details on how to use PWM channels.

The Jetson.GPIO library supports PWM only on pins with attached hardware PWM controllers. Unlike the RPi.GPIO library, the Jetson.GPIO library does not implement Software emulated PWM. Jetson Nano supports 2 PWM channels, and Jetson AGX Xavier supports 3 PWM channels. Jetson TX1 and TX2 do not support any PWM channels.

The system pinmux must be configured to connect the hardware PWM controlller(s) to the relevant pins. If the pinmux is not configured, PWM signals will not reach the pins! The Jetson.GPIO library does not dynamically modify the pinmux configuration to achieve this. Read the L4T documentation for details on how to configure the pinmux.

So I tried it with these preparations(flashing pinmux, installation).

But I can’t get the pulse…

Anyone please tell me suggestions ?

Preparations

1.Pinmux modification

pe6 {
				nvidia,pins = "pe6";
				nvidia,function = "pwm2";
				nvidia,pull = <0x0>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x0>;
			};

lcd_bl_pwm_pv0 {
				nvidia,pins = "lcd_bl_pwm_pv0";
				nvidia,function = "pwm0";
				nvidia,pull = <0x0>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x0>;
			};

gpio@6000d000 {
..............................

		default {
			gpio-hog;
			function;
			gpios = <0xc 0x0 0xd 0x0 0xe 0x0 0xf 0x0 0xd8 0x0 0xe8 0x0 0xa8 0x0 0x26 0x0 0x4d 0x0 0x4e 0x0 0x4c 0x0 0x4f 0x0>;
			gpio-input = <0xe8 0x95 0x5 0xbc 0xbd 0xbe 0xc1 0xc2 0xa9 0xc8 0xca 0x32 0x33 0x10 0x11 0x12 0x13 0x14 0x3a 0x3d 0x3e 0x41 0xe4>;
			gpio-output-low = <0x97 0x98 0xcb 0x38 0x3b 0x3c 0x3f 0x40 0x42>;
			gpio-output-high = <0x6 0xbb>;
			linux,phandle = <0x43>;
			phandle = <0x43>;
		};

This include SPI and I2S modifications.
In gpios, <0xa8 and 0x26> is <GPIO_PE6 and GPIO_PV00> , Is this correct ?

2.flashing DTB

dtc -I dts -O dtb -o edit.dtb ./edit.dts
sudo cp edit.dtb ~/kernel/dtb/tegra210-p3448-0000-p3449-0000-a02.dtb
sudo ~/Linux_for_Tegras/flash.sh --no-systemimg -k DTB jetson-nano-qspi-sd mmcblk0p1

reboot

  1. Installation Jetson.GPIO
    I used installation protocol by following jetson-gpio github page.
    jetson-gpio github page
    → README.md
    → Configuring the system

  2. Execution sample.py

Jetson.GPIO sample

sudo python3 samples/simple_pwm.py

GPIO is high.
But no pulse…

Result (from pin 33)

How configure to use PWM ?

Thanks.
devemin

2

This is tegra_gpio.

sudo cat /sys/kernel/debug/tegra_gpio
[sudo] password for masa: 
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 A: 0:0 64 40 40 04 00 00 000000
 B: 0:1 00 00 00 00 00 00 000000
 C: 0:2 1f 00 00 00 00 00 000000
 D: 0:3 00 00 00 00 00 00 000000
 E: 1:0 00 40 40 00 00 00 000000
 F: 1:1 00 00 00 00 00 00 000000
 G: 1:2 0c 00 00 04 00 00 000000
 H: 1:3 fd 99 00 60 00 00 000000
 I: 2:0 07 05 00 02 00 00 000000
 J: 2:1 00 00 00 00 00 00 000000
 K: 2:2 00 00 00 00 00 00 000000
 L: 2:3 00 00 00 00 00 00 000000
 M: 3:0 00 00 00 00 00 00 000000
 N: 3:1 00 00 00 00 00 00 000000
 O: 3:2 00 00 00 00 00 00 000000
 P: 3:3 00 00 00 00 00 00 000000
 Q: 4:0 00 00 00 00 00 00 000000
 R: 4:1 00 00 00 00 00 00 000000
 S: 4:2 a0 80 00 00 00 00 000000
 T: 4:3 01 01 00 00 00 00 000000
 U: 5:0 00 00 00 00 00 00 000000
 V: 5:1 02 00 00 02 00 00 000000
 W: 5:2 00 00 00 00 00 00 000000
 X: 5:3 78 08 08 30 00 60 606000
 Y: 6:0 06 00 00 02 00 00 000000
 Z: 6:1 0f 08 08 00 00 06 020600
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 00 00 00 00 00 00 000000
CC: 7:0 12 00 00 02 00 12 121200
DD: 7:1 00 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000
3

Anyone can tell me suggestions …please ??

I am repeating trial and error.

Maybe I can not use PWM feature ?

This is tegra_pinctrl_reg.

sudo cat /sys/kernel/debug/tegra_pinctrl_reg

Bank: 1 Reg: 0x70003000 Val: 0x00003040 -> sdmmc1_clk_pm0
Bank: 1 Reg: 0x70003004 Val: 0x00003048 -> sdmmc1_cmd_pm1
Bank: 1 Reg: 0x70003008 Val: 0x00003048 -> sdmmc1_dat3_pm2
Bank: 1 Reg: 0x7000300c Val: 0x00003048 -> sdmmc1_dat2_pm3
Bank: 1 Reg: 0x70003010 Val: 0x00003048 -> sdmmc1_dat1_pm4
Bank: 1 Reg: 0x70003014 Val: 0x00003048 -> sdmmc1_dat0_pm5
Bank: 1 Reg: 0x700032b4 Val: 0x00000000 -> sdmmc2_clk
Bank: 1 Reg: 0x700032b8 Val: 0x00000000 -> sdmmc2_clkb
Bank: 1 Reg: 0x700032bc Val: 0x00000000 -> sdmmc2_cmd
Bank: 1 Reg: 0x70003294 Val: 0x00000000 -> sdmmc2_dat0
Bank: 1 Reg: 0x70003298 Val: 0x00000000 -> sdmmc2_dat1
Bank: 1 Reg: 0x7000329c Val: 0x00000000 -> sdmmc2_dat2
Bank: 1 Reg: 0x700032a0 Val: 0x00000000 -> sdmmc2_dat3
Bank: 1 Reg: 0x700032a4 Val: 0x00000000 -> sdmmc2_dat4
Bank: 1 Reg: 0x700032a8 Val: 0x00000000 -> sdmmc2_dat5
Bank: 1 Reg: 0x700032ac Val: 0x00000000 -> sdmmc2_dat6
Bank: 1 Reg: 0x700032b0 Val: 0x00000000 -> sdmmc2_dat7
Bank: 1 Reg: 0x700032c0 Val: 0x00000000 -> sdmmc2_dqs
Bank: 1 Reg: 0x700032c4 Val: 0x00000000 -> sdmmc2_dqsb
Bank: 1 Reg: 0x7000301c Val: 0x00002040 -> sdmmc3_clk_pp0
Bank: 1 Reg: 0x70003020 Val: 0x00002048 -> sdmmc3_cmd_pp1
Bank: 1 Reg: 0x70003024 Val: 0x00002048 -> sdmmc3_dat0_pp5
Bank: 1 Reg: 0x70003028 Val: 0x00002048 -> sdmmc3_dat1_pp4
Bank: 1 Reg: 0x7000302c Val: 0x00002048 -> sdmmc3_dat2_pp3
Bank: 1 Reg: 0x70003030 Val: 0x00002048 -> sdmmc3_dat3_pp2
Bank: 1 Reg: 0x70003038 Val: 0x00000400 -> pex_l0_rst_n_pa0
Bank: 1 Reg: 0x7000303c Val: 0x00000450 -> pex_l0_clkreq_n_pa1
Bank: 1 Reg: 0x70003040 Val: 0x00000440 -> pex_wake_n_pa2
Bank: 1 Reg: 0x70003044 Val: 0x00000400 -> pex_l1_rst_n_pa3
Bank: 1 Reg: 0x70003048 Val: 0x00000440 -> pex_l1_clkreq_n_pa4
Bank: 1 Reg: 0x7000304c Val: 0x00000048 -> sata_led_active_pa5
Bank: 1 Reg: 0x7000304c Val: 0x00000048 -> pa5
Bank: 1 Reg: 0x70003050 Val: 0x0000e044 -> spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e044 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e044 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e048 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e048 -> spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006044 -> spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006044 -> spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006044 -> spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006044 -> spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006044 -> spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e014 -> spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e014 -> spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e014 -> spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e014 -> spi4_cs0_pc6
Bank: 1 Reg: 0x70003088 Val: 0x00000040 -> qspi_sck_pee0
Bank: 1 Reg: 0x7000308c Val: 0x00000000 -> qspi_cs_n_pee1
Bank: 1 Reg: 0x70003090 Val: 0x00000040 -> qspi_io0_pee2
Bank: 1 Reg: 0x70003094 Val: 0x00000040 -> qspi_io1_pee3
Bank: 1 Reg: 0x70003098 Val: 0x00000040 -> qspi_io2_pee4
Bank: 1 Reg: 0x7000309c Val: 0x00000040 -> qspi_io3_pee5
Bank: 1 Reg: 0x700030a4 Val: 0x00000041 -> dmic1_clk_pe0
Bank: 1 Reg: 0x700030a8 Val: 0x00000041 -> dmic1_dat_pe1
Bank: 1 Reg: 0x700030ac Val: 0x00000041 -> dmic2_clk_pe2
Bank: 1 Reg: 0x700030b0 Val: 0x00000041 -> dmic2_dat_pe3
Bank: 1 Reg: 0x700030b4 Val: 0x00000015 -> dmic3_clk_pe4
Bank: 1 Reg: 0x700030b8 Val: 0x00000015 -> dmic3_dat_pe5
Bank: 1 Reg: 0x700030bc Val: 0x00000440 -> gen1_i2c_scl_pj1
Bank: 1 Reg: 0x700030c0 Val: 0x00000440 -> gen1_i2c_sda_pj0
Bank: 1 Reg: 0x700030c4 Val: 0x00000440 -> gen2_i2c_scl_pj2
Bank: 1 Reg: 0x700030c8 Val: 0x00000440 -> gen2_i2c_sda_pj3
Bank: 1 Reg: 0x700030cc Val: 0x00000040 -> gen3_i2c_scl_pf0
Bank: 1 Reg: 0x700030d0 Val: 0x00000040 -> gen3_i2c_sda_pf1
Bank: 1 Reg: 0x700030d4 Val: 0x00000441 -> cam_i2c_scl_ps2
Bank: 1 Reg: 0x700030d8 Val: 0x00000441 -> cam_i2c_sda_ps3
Bank: 1 Reg: 0x700030dc Val: 0x00000040 -> pwr_i2c_scl_py3
Bank: 1 Reg: 0x700030e0 Val: 0x00000040 -> pwr_i2c_sda_py4
Bank: 1 Reg: 0x700030e4 Val: 0x00000000 -> uart1_tx_pu0
Bank: 1 Reg: 0x700030e8 Val: 0x00000040 -> uart1_rx_pu1
Bank: 1 Reg: 0x700030ec Val: 0x00000014 -> uart1_rts_pu2
Bank: 1 Reg: 0x700030f0 Val: 0x00000014 -> uart1_cts_pu3
Bank: 1 Reg: 0x700030f4 Val: 0x00000000 -> uart2_tx_pg0
Bank: 1 Reg: 0x700030f8 Val: 0x00000044 -> uart2_rx_pg1
Bank: 1 Reg: 0x700030fc Val: 0x00000047 -> uart2_rts_pg2
Bank: 1 Reg: 0x70003100 Val: 0x00000044 -> uart2_cts_pg3
Bank: 1 Reg: 0x70003104 Val: 0x00000000 -> uart3_tx_pd1
Bank: 1 Reg: 0x70003108 Val: 0x00000040 -> uart3_rx_pd2
Bank: 1 Reg: 0x7000310c Val: 0x00000008 -> uart3_rts_pd3
Bank: 1 Reg: 0x70003110 Val: 0x00000048 -> uart3_cts_pd4
Bank: 1 Reg: 0x70003114 Val: 0x00000000 -> uart4_tx_pi4
Bank: 1 Reg: 0x70003118 Val: 0x00000040 -> uart4_rx_pi5
Bank: 1 Reg: 0x7000311c Val: 0x00000000 -> uart4_rts_pi6
Bank: 1 Reg: 0x70003120 Val: 0x00000048 -> uart4_cts_pi7
Bank: 1 Reg: 0x70003124 Val: 0x00006054 -> dap1_fs_pb0
Bank: 1 Reg: 0x70003128 Val: 0x00006054 -> dap1_din_pb1
Bank: 1 Reg: 0x7000312c Val: 0x00006054 -> dap1_dout_pb2
Bank: 1 Reg: 0x70003130 Val: 0x00006054 -> dap1_sclk_pb3
Bank: 1 Reg: 0x70003134 Val: 0x00006040 -> dap2_fs_paa0
Bank: 1 Reg: 0x70003138 Val: 0x00006040 -> dap2_din_paa2
Bank: 1 Reg: 0x7000313c Val: 0x00006040 -> dap2_dout_paa3
Bank: 1 Reg: 0x70003140 Val: 0x00006040 -> dap2_sclk_paa1
Bank: 1 Reg: 0x70003144 Val: 0x00000044 -> dap4_fs_pj4
Bank: 1 Reg: 0x70003148 Val: 0x00000044 -> dap4_din_pj5
Bank: 1 Reg: 0x7000314c Val: 0x00000044 -> dap4_dout_pj6
Bank: 1 Reg: 0x70003150 Val: 0x00000044 -> dap4_sclk_pj7
Bank: 1 Reg: 0x70003154 Val: 0x00000000 -> cam1_mclk_ps0
Bank: 1 Reg: 0x70003158 Val: 0x00000000 -> cam2_mclk_ps1
Bank: 1 Reg: 0x7000315c Val: 0x00000000 -> jtag_rtck
Bank: 1 Reg: 0x70003160 Val: 0x00001000 -> clk_32k_in
Bank: 1 Reg: 0x70003164 Val: 0x00000015 -> clk_32k_out_py5
Bank: 1 Reg: 0x70003168 Val: 0x00000550 -> batt_bcl
Bank: 1 Reg: 0x7000316c Val: 0x00000004 -> clk_req
Bank: 1 Reg: 0x70003170 Val: 0x00000004 -> cpu_pwr_req
Bank: 1 Reg: 0x70003174 Val: 0x00000048 -> pwr_int_n
Bank: 1 Reg: 0x70003178 Val: 0x00000000 -> shutdown
Bank: 1 Reg: 0x7000317c Val: 0x00000000 -> core_pwr_req
Bank: 1 Reg: 0x70003180 Val: 0x00000048 -> aud_mclk_pbb0
Bank: 1 Reg: 0x70003184 Val: 0x00000001 -> dvfs_pwm_pbb1
Bank: 1 Reg: 0x70003188 Val: 0x00000014 -> dvfs_clk_pbb2
Bank: 1 Reg: 0x7000318c Val: 0x00000014 -> gpio_x1_aud_pbb3
Bank: 1 Reg: 0x70003190 Val: 0x00000014 -> gpio_x3_aud_pbb4
Bank: 1 Reg: 0x70003194 Val: 0x00000114 -> pcc7
Bank: 1 Reg: 0x70003198 Val: 0x00000540 -> hdmi_cec_pcc0
Bank: 1 Reg: 0x7000319c Val: 0x00000140 -> hdmi_int_dp_hpd_pcc1
Bank: 1 Reg: 0x700031a0 Val: 0x00000014 -> spdif_out_pcc2
Bank: 1 Reg: 0x700031a4 Val: 0x00000014 -> spdif_in_pcc3
Bank: 1 Reg: 0x700031a8 Val: 0x00000148 -> usb_vbus_en0_pcc4
Bank: 1 Reg: 0x700031ac Val: 0x00000114 -> usb_vbus_en1_pcc5
Bank: 1 Reg: 0x700031b0 Val: 0x00000040 -> dp_hpd0_pcc6
Bank: 1 Reg: 0x700031b4 Val: 0x00000000 -> wifi_en_ph0
Bank: 1 Reg: 0x700031b8 Val: 0x00000014 -> wifi_rst_ph1
Bank: 1 Reg: 0x700031bc Val: 0x00000044 -> wifi_wake_ap_ph2
Bank: 1 Reg: 0x700031c0 Val: 0x00000000 -> ap_wake_bt_ph3
Bank: 1 Reg: 0x700031c4 Val: 0x00000000 -> bt_rst_ph4
Bank: 1 Reg: 0x700031c8 Val: 0x00000048 -> bt_wake_ap_ph5
Bank: 1 Reg: 0x700031cc Val: 0x00000000 -> ap_wake_nfc_ph7
Bank: 1 Reg: 0x700031d0 Val: 0x00000000 -> nfc_en_pi0
Bank: 1 Reg: 0x700031d4 Val: 0x00000044 -> nfc_int_pi1
Bank: 1 Reg: 0x700031d8 Val: 0x00000000 -> gps_en_pi2
Bank: 1 Reg: 0x700031dc Val: 0x00000014 -> gps_rst_pi3
Bank: 1 Reg: 0x700031e0 Val: 0x00000014 -> cam_rst_ps4
Bank: 1 Reg: 0x700031e4 Val: 0x00000048 -> cam_af_en_ps5
Bank: 1 Reg: 0x700031e8 Val: 0x00000015 -> cam_flash_en_ps6
Bank: 1 Reg: 0x700031ec Val: 0x00000000 -> cam1_pwdn_ps7
Bank: 1 Reg: 0x700031f0 Val: 0x00000000 -> cam2_pwdn_pt0
Bank: 1 Reg: 0x700031f4 Val: 0x00000014 -> cam1_strobe_pt1
Bank: 1 Reg: 0x700031f8 Val: 0x00000044 -> lcd_te_py2
Bank: 1 Reg: 0x700031fc Val: 0x00000047 -> lcd_bl_pwm_pv0
Bank: 1 Reg: 0x70003200 Val: 0x00000040 -> lcd_bl_en_pv1
Bank: 1 Reg: 0x70003204 Val: 0x00000014 -> lcd_rst_pv2
Bank: 1 Reg: 0x70003208 Val: 0x00000014 -> lcd_gpio1_pv3
Bank: 1 Reg: 0x7000320c Val: 0x00000001 -> lcd_gpio2_pv4
Bank: 1 Reg: 0x70003210 Val: 0x00000014 -> ap_ready_pv5
Bank: 1 Reg: 0x70003214 Val: 0x00000014 -> touch_rst_pv6
Bank: 1 Reg: 0x70003218 Val: 0x00000014 -> touch_clk_pv7
Bank: 1 Reg: 0x7000321c Val: 0x00000014 -> modem_wake_ap_px0
Bank: 1 Reg: 0x70003220 Val: 0x00000014 -> touch_int_px1
Bank: 1 Reg: 0x70003224 Val: 0x00000014 -> motion_int_px2
Bank: 1 Reg: 0x70003228 Val: 0x00000000 -> als_prox_int_px3
Bank: 1 Reg: 0x7000322c Val: 0x00000048 -> temp_alert_px4
Bank: 1 Reg: 0x70003230 Val: 0x00000048 -> button_power_on_px5
Bank: 1 Reg: 0x70003234 Val: 0x00000048 -> button_vol_up_px6
Bank: 1 Reg: 0x70003238 Val: 0x00000014 -> button_vol_down_px7
Bank: 1 Reg: 0x7000323c Val: 0x00000014 -> button_slide_sw_py0
Bank: 1 Reg: 0x70003240 Val: 0x00000048 -> button_home_py1
Bank: 1 Reg: 0x70003244 Val: 0x00000000 -> pa6
Bank: 1 Reg: 0x70003248 Val: 0x00000044 -> pe6
Bank: 1 Reg: 0x7000324c Val: 0x00000002 -> pe7
Bank: 1 Reg: 0x70003250 Val: 0x00000048 -> ph6
Bank: 1 Reg: 0x70003254 Val: 0x00006015 -> pk0
Bank: 1 Reg: 0x70003258 Val: 0x00006015 -> pk1
Bank: 1 Reg: 0x7000325c Val: 0x00006015 -> pk2
Bank: 1 Reg: 0x70003260 Val: 0x00006015 -> pk3
Bank: 1 Reg: 0x70003264 Val: 0x00006014 -> pk4
Bank: 1 Reg: 0x70003268 Val: 0x00006014 -> pk5
Bank: 1 Reg: 0x7000326c Val: 0x00006014 -> pk6
Bank: 1 Reg: 0x70003270 Val: 0x00006014 -> pk7
Bank: 1 Reg: 0x70003274 Val: 0x00006014 -> pl0
Bank: 1 Reg: 0x70003278 Val: 0x00006014 -> pl1
Bank: 1 Reg: 0x7000327c Val: 0x00000048 -> pz0
Bank: 1 Reg: 0x70003280 Val: 0x00000049 -> pz1
Bank: 1 Reg: 0x70003284 Val: 0x00000048 -> pz2
Bank: 1 Reg: 0x70003288 Val: 0x00000001 -> pz3
Bank: 1 Reg: 0x7000328c Val: 0x00000014 -> pz4
Bank: 1 Reg: 0x70003290 Val: 0x00000048 -> pz5
Bank: 0 Reg: 0x700009c0 Val: 0x00000000 -> drive_pa6
Bank: 0 Reg: 0x700009c4 Val: 0x00000000 -> drive_pcc7
Bank: 0 Reg: 0x700009c8 Val: 0x00000000 -> drive_pe6
Bank: 0 Reg: 0x700009cc Val: 0x00000000 -> drive_pe7
Bank: 0 Reg: 0x700009d0 Val: 0x00000000 -> drive_ph6
Bank: 0 Reg: 0x700009d4 Val: 0x00000000 -> drive_pk0
Bank: 0 Reg: 0x700009d8 Val: 0x00000000 -> drive_pk1
Bank: 0 Reg: 0x700009dc Val: 0x00000000 -> drive_pk2
Bank: 0 Reg: 0x700009e0 Val: 0x00000000 -> drive_pk3
Bank: 0 Reg: 0x700009e4 Val: 0x00000000 -> drive_pk4
Bank: 0 Reg: 0x700009e8 Val: 0x00000000 -> drive_pk5
Bank: 0 Reg: 0x700009ec Val: 0x00000000 -> drive_pk6
Bank: 0 Reg: 0x700009f0 Val: 0x00000000 -> drive_pk7
Bank: 0 Reg: 0x700009f4 Val: 0x00000000 -> drive_pl0
Bank: 0 Reg: 0x700009f8 Val: 0x00000000 -> drive_pl1
Bank: 0 Reg: 0x700009fc Val: 0x01010000 -> drive_pz0
Bank: 0 Reg: 0x70000a00 Val: 0x01010000 -> drive_pz1
Bank: 0 Reg: 0x70000a04 Val: 0x00000000 -> drive_pz2
Bank: 0 Reg: 0x70000a08 Val: 0x00000000 -> drive_pz3
Bank: 0 Reg: 0x70000a0c Val: 0x00000000 -> drive_pz4
Bank: 0 Reg: 0x70000a10 Val: 0x00000000 -> drive_pz5
Bank: 0 Reg: 0x70000a98 Val: 0x51115000 -> drive_sdmmc1
Bank: 0 Reg: 0x70000a9c Val: 0x07ffd040 -> drive_sdmmc2
Bank: 0 Reg: 0x70000ab0 Val: 0x51212000 -> drive_sdmmc3
Bank: 0 Reg: 0x70000ab4 Val: 0x07ffd040 -> drive_sdmmc4
Bank: 0 Reg: 0x70000b70 Val: 0x00000001 -> drive_qspi_comp_control
Bank: 0 Reg: 0x70000b78 Val: 0x00000001 -> drive_qspi_lpbk_control
Bank: 0 Reg: 0x70000a78 Val: 0x00808000 -> drive_qspi_comp

This is pinmux-functions

sudo cat /sys/kernel/debug/pinctrl/700008d4.pinmux/pinmux-functions

function: aud, groups = [ aud_mclk_pbb0 ]
function: bcl, groups = [ batt_bcl ]
function: blink, groups = [ clk_32k_out_py5 ]
function: ccla, groups = [ pz2 ]
function: cec, groups = [ hdmi_cec_pcc0 ]
function: cldvfs, groups = [ dvfs_pwm_pbb1 dvfs_clk_pbb2 ]
function: clk, groups = [ clk_32k_in ]
function: core, groups = [ core_pwr_req ]
function: cpu, groups = [ cpu_pwr_req ]
function: displaya, groups = [ lcd_te_py2 lcd_bl_pwm_pv0 ]
function: displayb, groups = [ lcd_gpio1_pv3 lcd_gpio2_pv4 ]
function: dmic1, groups = [ dmic1_clk_pe0 dmic1_dat_pe1 ]
function: dmic2, groups = [ dmic2_clk_pe2 dmic2_dat_pe3 ]
function: dmic3, groups = [ dmic3_clk_pe4 dmic3_dat_pe5 ]
function: dp, groups = [ hdmi_int_dp_hpd_pcc1 dp_hpd0_pcc6 ]
function: dtv, groups = [ spi2_mosi_pb4 spi2_miso_pb5 spi2_sck_pb6 spi2_cs0_pb7 ]
function: extperiph3, groups = [ cam1_mclk_ps0 cam2_mclk_ps1 ]
function: i2c1, groups = [ gen1_i2c_scl_pj1 gen1_i2c_sda_pj0 ]
function: i2c2, groups = [ gen2_i2c_scl_pj2 gen2_i2c_sda_pj3 ]
function: i2c3, groups = [ gen3_i2c_scl_pf0 gen3_i2c_sda_pf1 cam_i2c_scl_ps2 cam_i2c_sda_ps3 ]
function: i2cpmu, groups = [ pwr_i2c_scl_py3 pwr_i2c_sda_py4 ]
function: i2cvi, groups = [ cam_i2c_scl_ps2 cam_i2c_sda_ps3 ]
function: i2s1, groups = [ dap1_fs_pb0 dap1_din_pb1 dap1_dout_pb2 dap1_sclk_pb3 ]
function: i2s2, groups = [ dap2_fs_paa0 dap2_din_paa2 dap2_dout_paa3 dap2_sclk_paa1 ]
function: i2s3, groups = [ dmic1_clk_pe0 dmic1_dat_pe1 dmic2_clk_pe2 dmic2_dat_pe3 ]
function: i2s4a, groups = [ uart2_tx_pg0 uart2_rx_pg1 uart2_rts_pg2 uart2_cts_pg3 ]
function: i2s4b, groups = [ dap4_fs_pj4 dap4_din_pj5 dap4_dout_pj6 dap4_sclk_pj7 ]
function: i2s5a, groups = [ dmic3_clk_pe4 dmic3_dat_pe5 pe6 pe7 ]
function: i2s5b, groups = [ pk0 pk1 pk2 pk3 ]
function: iqc0, groups = [ pk0 pk1 pk2 pk3 ]
function: iqc1, groups = [ pk4 pk5 pk6 pk7 ]
function: jtag, groups = [ jtag_rtck ]
function: pe, groups = [ pex_wake_n_pa2 ]
function: pe0, groups = [ pex_l0_rst_n_pa0 pex_l0_clkreq_n_pa1 ]
function: pe1, groups = [ pex_l1_rst_n_pa3 pex_l1_clkreq_n_pa4 ]
function: pmi, groups = [ pwr_int_n ]
function: pwm0, groups = [ lcd_bl_pwm_pv0 ]
function: pwm1, groups = [ lcd_gpio2_pv4 ]
function: pwm2, groups = [ pe6 ]
function: pwm3, groups = [ pe7 ]
function: qspi, groups = [ qspi_sck_pee0 qspi_cs_n_pee1 qspi_io0_pee2 qspi_io1_pee3 qspi_io2_pee4 qspi_io3_pee5 ]
function: rsvd0, groups = [ pa5 dvfs_pwm_pbb1 dvfs_clk_pbb2 gpio_x1_aud_pbb3 gpio_x3_aud_pbb4 pcc7 wifi_en_ph0 wifi_rst_ph1 wifi_wake_ap_ph2 ap_wake_bt_ph3 bt_rst_ph4 bt_wake_ap_ph5 ap_wake_nfc_ph7 nfc_en_pi0 nfc_int_pi1 gps_en_pi2 gps_rst_pi3 lcd_bl_en_pv1 lcd_rst_pv2 ap_ready_pv5 touch_rst_pv6 modem_wake_ap_px0 touch_int_px1 motion_int_px2 als_prox_int_px3 temp_alert_px4 button_power_on_px5 button_vol_up_px6 button_vol_down_px7 button_slide_sw_py0 button_home_py1 pe6 pe7 ph6 pl0 ]
function: rsvd1, groups = [ sdmmc1_clk_pm0 sdmmc1_dat0_pm5 sdmmc2_clk sdmmc2_clkb sdmmc2_cmd sdmmc2_dat0 sdmmc2_dat1 sdmmc2_dat2 sdmmc2_dat3 sdmmc2_dat4 sdmmc2_dat5 sdmmc2_dat6 sdmmc2_dat7 sdmmc2_dqs sdmmc2_dqsb sdmmc3_clk_pp0 sdmmc3_cmd_pp1 sdmmc3_dat0_pp5 sdmmc3_dat1_pp4 sdmmc3_dat2_pp3 sdmmc3_dat3_pp2 pex_l0_rst_n_pa0 pex_l0_clkreq_n_pa1 pex_wake_n_pa2 pex_l1_rst_n_pa3 pex_l1_clkreq_n_pa4 sata_led_active_pa5 pa5 spi1_mosi_pc0 spi1_miso_pc1 spi1_sck_pc2 spi1_cs0_pc3 spi1_cs1_pc4 spi2_cs1_pdd0 spi4_mosi_pc7 spi4_miso_pd0 spi4_sck_pc5 spi4_cs0_pc6 qspi_sck_pee0 qspi_cs_n_pee1 qspi_io0_pee2 qspi_io1_pee3 qspi_io2_pee4 qspi_io3_pee5 gen1_i2c_scl_pj1 gen1_i2c_sda_pj0 gen2_i2c_scl_pj2 gen2_i2c_sda_pj3 gen3_i2c_scl_pf0 gen3_i2c_sda_pf1 pwr_i2c_scl_py3 pwr_i2c_sda_py4 uart1_tx_pu0 uart1_rx_pu1 uart1_rts_pu2 uart1_cts_pu3 dap1_fs_pb0 dap1_din_pb1 dap1_dout_pb2 dap1_sclk_pb3 dap2_fs_paa0 dap2_din_paa2 dap2_dout_paa3 dap2_sclk_paa1 dap4_fs_pj4 dap4_din_pj5 dap4_dout_pj6 dap4_sclk_pj7 cam1_mclk_ps0 cam2_mclk_ps1 jtag_rtck clk_32k_in batt_bcl clk_req cpu_pwr_req pwr_int_n shutdown core_pwr_req aud_mclk_pbb0 gpio_x1_aud_pbb3 gpio_x3_aud_pbb4 pcc7 hdmi_cec_pcc0 hdmi_int_dp_hpd_pcc1 spdif_out_pcc2 spdif_in_pcc3 usb_vbus_en0_pcc4 usb_vbus_en1_pcc5 dp_hpd0_pcc6 wifi_en_ph0 wifi_rst_ph1 wifi_wake_ap_ph2 bt_wake_ap_ph5 ap_wake_nfc_ph7 nfc_en_pi0 nfc_int_pi1 gps_en_pi2 gps_rst_pi3 cam_rst_ps4 cam1_pwdn_ps7 cam2_pwdn_pt0 cam1_strobe_pt1 lcd_te_py2 lcd_bl_en_pv1 lcd_rst_pv2 lcd_gpio1_pv3 ap_ready_pv5 touch_rst_pv6 touch_clk_pv7 modem_wake_ap_px0 touch_int_px1 motion_int_px2 als_prox_int_px3 temp_alert_px4 button_power_on_px5 button_vol_up_px6 button_vol_down_px7 button_slide_sw_py0 button_home_py1 pa6 ph6 pk4 pk5 pk6 pk7 pl0 pl1 pz0 pz3 pz4 pz5 ]
function: rsvd2, groups = [ sdmmc1_clk_pm0 sdmmc1_cmd_pm1 sdmmc1_dat3_pm2 sdmmc1_dat2_pm3 sdmmc1_dat1_pm4 sdmmc1_dat0_pm5 sdmmc2_clk sdmmc2_clkb sdmmc2_cmd sdmmc2_dat0 sdmmc2_dat1 sdmmc2_dat2 sdmmc2_dat3 sdmmc2_dat4 sdmmc2_dat5 sdmmc2_dat6 sdmmc2_dat7 sdmmc2_dqs sdmmc2_dqsb sdmmc3_clk_pp0 sdmmc3_cmd_pp1 sdmmc3_dat0_pp5 sdmmc3_dat1_pp4 sdmmc3_dat2_pp3 sdmmc3_dat3_pp2 pex_l0_rst_n_pa0 pex_l0_clkreq_n_pa1 pex_wake_n_pa2 pex_l1_rst_n_pa3 pex_l1_clkreq_n_pa4 sata_led_active_pa5 pa5 spi1_mosi_pc0 spi1_miso_pc1 spi1_sck_pc2 spi1_cs0_pc3 spi1_cs1_pc4 spi2_mosi_pb4 spi2_miso_pb5 spi2_sck_pb6 spi2_cs0_pb7 spi2_cs1_pdd0 spi4_mosi_pc7 spi4_miso_pd0 spi4_sck_pc5 spi4_cs0_pc6 qspi_sck_pee0 qspi_cs_n_pee1 qspi_io0_pee2 qspi_io1_pee3 qspi_io2_pee4 qspi_io3_pee5 dmic1_clk_pe0 dmic1_dat_pe1 dmic2_clk_pe2 dmic2_dat_pe3 dmic3_clk_pe4 dmic3_dat_pe5 gen1_i2c_scl_pj1 gen1_i2c_sda_pj0 gen2_i2c_scl_pj2 gen2_i2c_sda_pj3 gen3_i2c_scl_pf0 gen3_i2c_sda_pf1 cam_i2c_scl_ps2 cam_i2c_sda_ps3 pwr_i2c_scl_py3 pwr_i2c_sda_py4 uart1_tx_pu0 uart1_rx_pu1 uart1_rts_pu2 uart1_cts_pu3 uart2_rts_pg2 uart2_cts_pg3 uart3_tx_pd1 uart3_rx_pd2 uart3_rts_pd3 uart3_cts_pd4 uart4_tx_pi4 uart4_rx_pi5 uart4_rts_pi6 uart4_cts_pi7 dap1_fs_pb0 dap1_din_pb1 dap1_dout_pb2 dap1_sclk_pb3 dap2_fs_paa0 dap2_din_paa2 dap2_dout_paa3 dap2_sclk_paa1 dap4_fs_pj4 dap4_din_pj5 dap4_dout_pj6 dap4_sclk_pj7 cam1_mclk_ps0 cam2_mclk_ps1 jtag_rtck clk_32k_in clk_32k_out_py5 batt_bcl clk_req cpu_pwr_req pwr_int_n shutdown core_pwr_req aud_mclk_pbb0 pcc7 hdmi_cec_pcc0 hdmi_int_dp_hpd_pcc1 spdif_out_pcc2 spdif_in_pcc3 usb_vbus_en0_pcc4 usb_vbus_en1_pcc5 dp_hpd0_pcc6 wifi_en_ph0 wifi_rst_ph1 wifi_wake_ap_ph2 bt_wake_ap_ph5 ap_wake_nfc_ph7 nfc_en_pi0 nfc_int_pi1 gps_en_pi2 gps_rst_pi3 cam_rst_ps4 cam_af_en_ps5 cam_flash_en_ps6 cam1_pwdn_ps7 cam2_pwdn_pt0 cam1_strobe_pt1 lcd_te_py2 lcd_bl_en_pv1 lcd_rst_pv2 lcd_gpio1_pv3 lcd_gpio2_pv4 ap_ready_pv5 touch_rst_pv6 touch_clk_pv7 modem_wake_ap_px0 touch_int_px1 motion_int_px2 als_prox_int_px3 temp_alert_px4 button_power_on_px5 button_vol_up_px6 button_vol_down_px7 button_slide_sw_py0 button_home_py1 pa6 ph6 pk0 pk1 pk2 pk3 pk4 pk5 pk6 pk7 pl0 pl1 pz0 pz1 pz2 pz3 pz4 pz5 ]
function: rsvd3, groups = [ sdmmc1_clk_pm0 sdmmc1_cmd_pm1 sdmmc1_dat3_pm2 sdmmc1_dat2_pm3 sdmmc1_dat1_pm4 sdmmc1_dat0_pm5 sdmmc2_clk sdmmc2_clkb sdmmc2_cmd sdmmc2_dat0 sdmmc2_dat1 sdmmc2_dat2 sdmmc2_dat3 sdmmc2_dat4 sdmmc2_dat5 sdmmc2_dat6 sdmmc2_dat7 sdmmc2_dqs sdmmc2_dqsb sdmmc3_clk_pp0 sdmmc3_cmd_pp1 sdmmc3_dat0_pp5 sdmmc3_dat1_pp4 sdmmc3_dat2_pp3 sdmmc3_dat3_pp2 pex_l0_rst_n_pa0 pex_l0_clkreq_n_pa1 pex_wake_n_pa2 pex_l1_rst_n_pa3 pex_l1_clkreq_n_pa4 sata_led_active_pa5 pa5 spi1_mosi_pc0 spi1_miso_pc1 spi1_sck_pc2 spi1_cs0_pc3 spi1_cs1_pc4 spi2_mosi_pb4 spi2_miso_pb5 spi2_sck_pb6 spi2_cs0_pb7 spi2_cs1_pdd0 spi4_mosi_pc7 spi4_miso_pd0 spi4_sck_pc5 spi4_cs0_pc6 qspi_sck_pee0 qspi_cs_n_pee1 qspi_io0_pee2 qspi_io1_pee3 qspi_io2_pee4 qspi_io3_pee5 dmic1_clk_pe0 dmic1_dat_pe1 dmic2_clk_pe2 dmic2_dat_pe3 dmic3_clk_pe4 dmic3_dat_pe5 gen1_i2c_scl_pj1 gen1_i2c_sda_pj0 gen2_i2c_scl_pj2 gen2_i2c_sda_pj3 gen3_i2c_scl_pf0 gen3_i2c_sda_pf1 cam_i2c_scl_ps2 cam_i2c_sda_ps3 pwr_i2c_scl_py3 pwr_i2c_sda_py4 uart1_tx_pu0 uart1_rx_pu1 uart1_rts_pu2 uart1_cts_pu3 uart3_tx_pd1 uart3_rx_pd2 uart3_rts_pd3 uart3_cts_pd4 uart4_tx_pi4 uart4_rx_pi5 uart4_rts_pi6 uart4_cts_pi7 dap1_fs_pb0 dap1_din_pb1 dap1_dout_pb2 dap1_sclk_pb3 dap2_fs_paa0 dap2_din_paa2 dap2_dout_paa3 dap2_sclk_paa1 dap4_fs_pj4 dap4_din_pj5 dap4_dout_pj6 dap4_sclk_pj7 cam1_mclk_ps0 cam2_mclk_ps1 jtag_rtck clk_32k_in clk_32k_out_py5 batt_bcl clk_req cpu_pwr_req pwr_int_n shutdown core_pwr_req aud_mclk_pbb0 dvfs_pwm_pbb1 dvfs_clk_pbb2 gpio_x1_aud_pbb3 gpio_x3_aud_pbb4 pcc7 hdmi_cec_pcc0 hdmi_int_dp_hpd_pcc1 spdif_out_pcc2 spdif_in_pcc3 usb_vbus_en0_pcc4 usb_vbus_en1_pcc5 dp_hpd0_pcc6 wifi_en_ph0 wifi_rst_ph1 wifi_wake_ap_ph2 ap_wake_bt_ph3 bt_rst_ph4 bt_wake_ap_ph5 ap_wake_nfc_ph7 nfc_en_pi0 nfc_int_pi1 gps_en_pi2 gps_rst_pi3 cam_rst_ps4 cam_af_en_ps5 cam_flash_en_ps6 cam1_pwdn_ps7 cam2_pwdn_pt0 cam1_strobe_pt1 lcd_te_py2 lcd_bl_pwm_pv0 lcd_bl_en_pv1 lcd_rst_pv2 lcd_gpio1_pv3 ap_ready_pv5 touch_rst_pv6 touch_clk_pv7 modem_wake_ap_px0 touch_int_px1 motion_int_px2 als_prox_int_px3 temp_alert_px4 button_power_on_px5 button_vol_up_px6 button_vol_down_px7 button_slide_sw_py0 button_home_py1 pa6 pe6 pe7 ph6 pk0 pk1 pk2 pk3 pk4 pk5 pk6 pk7 pl0 pl1 pz0 pz1 pz2 pz3 pz4 pz5 ]
function: sata, groups = [ sata_led_active_pa5 pa6 ]
function: sdmmc1, groups = [ sdmmc1_clk_pm0 sdmmc1_cmd_pm1 sdmmc1_dat3_pm2 sdmmc1_dat2_pm3 sdmmc1_dat1_pm4 sdmmc1_dat0_pm5 pz1 pz4 ]
function: sdmmc2, groups = [ sdmmc2_clk sdmmc2_clkb sdmmc2_cmd sdmmc2_dat0 sdmmc2_dat1 sdmmc2_dat2 sdmmc2_dat3 sdmmc2_dat4 sdmmc2_dat5 sdmmc2_dat6 sdmmc2_dat7 sdmmc2_dqs sdmmc2_dqsb ]
function: sdmmc3, groups = [ sdmmc3_clk_pp0 sdmmc3_cmd_pp1 sdmmc3_dat0_pp5 sdmmc3_dat1_pp4 sdmmc3_dat2_pp3 sdmmc3_dat3_pp2 pz2 pz3 ]
function: shutdown, groups = [ shutdown ]
function: soc, groups = [ clk_32k_out_py5 pl1 pz5 ]
function: sor0, groups = [ lcd_bl_pwm_pv0 ]
function: sor1, groups = [ lcd_gpio2_pv4 ]
function: spdif, groups = [ uart2_tx_pg0 uart2_rx_pg1 spdif_out_pcc2 spdif_in_pcc3 ap_wake_bt_ph3 bt_rst_ph4 ]
function: spi1, groups = [ spi1_mosi_pc0 spi1_miso_pc1 spi1_sck_pc2 spi1_cs0_pc3 spi1_cs1_pc4 ]
function: spi2, groups = [ spi2_mosi_pb4 spi2_miso_pb5 spi2_sck_pb6 spi2_cs0_pb7 spi2_cs1_pdd0 ]
function: spi3, groups = [ sdmmc1_cmd_pm1 sdmmc1_dat3_pm2 sdmmc1_dat2_pm3 sdmmc1_dat1_pm4 dvfs_pwm_pbb1 dvfs_clk_pbb2 gpio_x1_aud_pbb3 gpio_x3_aud_pbb4 ]
function: spi4, groups = [ spi4_mosi_pc7 spi4_miso_pd0 spi4_sck_pc5 spi4_cs0_pc6 uart3_tx_pd1 uart3_rx_pd2 uart3_rts_pd3 uart3_cts_pd4 ]
function: sys, groups = [ clk_req ]
function: touch, groups = [ touch_clk_pv7 ]
function: uart, groups = [ uart2_tx_pg0 uart2_rx_pg1 uart2_rts_pg2 uart2_cts_pg3 uart4_tx_pi4 uart4_rx_pi5 uart4_rts_pi6 uart4_cts_pi7 ]
function: uarta, groups = [ uart1_tx_pu0 uart1_rx_pu1 uart1_rts_pu2 uart1_cts_pu3 ]
function: uartb, groups = [ uart2_tx_pg0 uart2_rx_pg1 uart2_rts_pg2 uart2_cts_pg3 ap_wake_bt_ph3 bt_rst_ph4 ]
function: uartc, groups = [ uart3_tx_pd1 uart3_rx_pd2 uart3_rts_pd3 uart3_cts_pd4 ]
function: uartd, groups = [ uart4_tx_pi4 uart4_rx_pi5 uart4_rts_pi6 uart4_cts_pi7 ]
function: usb, groups = [ usb_vbus_en0_pcc4 usb_vbus_en1_pcc5 ]
function: vgp1, groups = [ cam_rst_ps4 ]
function: vgp2, groups = [ cam_af_en_ps5 ]
function: vgp3, groups = [ cam_flash_en_ps6 ]
function: vgp4, groups = [ cam1_pwdn_ps7 ]
function: vgp5, groups = [ cam2_pwdn_pt0 ]
function: vgp6, groups = [ cam1_strobe_pt1 ]
function: vimclk, groups = [ cam_af_en_ps5 cam_flash_en_ps6 ]
function: vimclk2, groups = [ pz0 pz1 ]

In progress, this is /sys/kernel/debug/pwm

sudo python3 samples/simple_pwm.py &

sudo cat /sys/kernel/debug/pwm

platform/70110000.pwm, 1 PWM device
 pwm-0   (pwm-regulator       ): requested enabled period: 2500 ns duty: 0 ns polarity: normal

platform/7000a000.pwm, 4 PWM devices
 pwm-0   (lightbar            ): requested enabled period: 10000000 ns duty: 10000000 ns polarity: normal
 pwm-1   (pwm-regulator       ): requested enabled period: 8000 ns duty: 1440 ns polarity: normal
 pwm-2   (sysfs               ): requested enabled period: 20000000 ns duty: 5000000 ns polarity: normal
 pwm-3   (pwm-fan             ): requested enabled period: 45334 ns duty: 0 ns polarity: normal

2019-06-28 (1).png
2019-06-28 (1).png1002×752 18.5 KB

4

hello devemin,

Jetson Nano Software Features show PWM is supported.
please also refer to similar issue, Topic 1056245.
thanks

5

Thanks for reply, JerryChang.

I saw the topic (1056245 [url]https://devtalk.nvidia.com/default/topic/1056245/[/url]).
And I searched for many PWM’s topics at this forum too.
But I could not get beneficial information…

I do not know how to investigate this problem, and what is wrong about my operation…
I want the normal operation list with working PWM (or working properly device-tree file).

Could you give me some more tips?

thanks.

6

Hi devemin,

Did you verify your device-tree changes in your filesystem?

You can verify DTB build time:

dmesg | grep DTB

You can check if “nvidia,function” is “pwm2” to make sure your change was applied.

cat /proc/device-tree/pinmux@700008d4/common/pe6/nvidia,function

If your changes are not applied, I recommend you to download L4T sources, perform the device-tree modifications, then compile and flash the device-tree.

Probably you will need to modify one of the following files:

hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-a02.dtsi
hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-a00.dtsi
hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-a01.dtsi
hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0002-a02.dtsi

Find here a guide to build Jetson Nano L4T source:
https://developer.ridgerun.com/wiki/index.php?title=NVIDIA_Jetson_Nano_-_Building_the_Kernel_from_Source

Regards,
-Enrique

7

Hi EnrigueR.

Oh thanks! You gave me a pathway to going forward!

But I think that my changes are applied. No pulse.

I connected the oscilloscope to the GPIO with [+: No.33 gpio, -: GND]
(There is a picture at attachment file.)

Should I try to compile from sourcefile?

I will try it later. (But I think it will get same result. )

Is there another way to check the problem ?

thanks.
devemin

dmesg | grep DTB
DTB Build time: May 13 2019 18:39:12

-> It was same as the description inside my dts file. it's not defaut ( not March ).

cat /proc/device-tree/pinmux@700008d4/common/pe6/nvidia,function

pwm2

sudo su

root@xxxxjetson2:/sys/devices/7000a000.pwm/pwm/<b>pwmchip0</b># echo 2 > export 
root@xxxxjetson2:/sys/devices/7000a000.pwm/pwm/<b>pwmchip0</b># cd ./pwm2
root@xxxxjetson2:/sys/devices/7000a000.pwm/pwm/pwmchip0/pwm2# echo 10000000 > period 
root@xxxxjetson2:/sys/devices/7000a000.pwm/pwm/pwmchip0/pwm2# echo 5000000 > duty_cycle 
root@xxxxjetson2:/sys/devices/7000a000.pwm/pwm/pwmchip0/pwm2# echo 1 > enable

root@xxxxjetson2:/sys/devices/7000a000.pwm/pwm/pwmchip0/pwm2# cat /sys/kernel/debug/pwm
platform/70110000.pwm, 1 PWM device
 pwm-0   (pwm-regulator       ): requested enabled period: 2500 ns duty: 0 ns polarity: normal

platform/7000a000.pwm, 4 PWM devices
 pwm-0   (lightbar            ): requested enabled period: 10000000 ns duty: 10000000 ns polarity: normal
 pwm-1   (pwm-regulator       ): requested enabled period: 8000 ns duty: 1440 ns polarity: normal
 pwm-2   (sysfs               ): requested enabled period: 10000000 ns duty: 5000000 ns polarity: normal
 pwm-3   (pwm-fan             ): requested enabled period: 45334 ns duty: 45135 ns polarity: normal

I don’t know next ways…

Why are there 2 paths “pwmchip0” and “pwmchip4” ?

I used “pwmchip0”. I could not change the “pwmchip4”'s options.

DSC_6225.JPG
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DSC_6225.JPG
DSC_6225.JPG1652×929 399 KB

8

hello

I gave up to use PWM.

I changed the settings for pull-register(up/down), but no pulse at pulse-analyzer screen.

And other changes didn’t make no pulse.

Thanks for reading.

devemin

9

Hi devemin,

From what pin are you measuring the PWM output?

The correct pin of J41 expansion header is number 22.

You can find the following definition in Pinmux Config Template:

PW3_PWM2 → GPIO_PE6 → GPIO13

And according to J41 Header Pinout ([url]https://www.jetsonhacks.com/nvidia-jetson-nano-j41-header-pinout/[/url]):

GPIO13 → Pinout 22

Regards,
-Enrique

10

hello EnriqueR.

Wow thanks a lot for reply!

I read the pinout list.

And I checked the pinmux’s spreadsheet from NVIDIA’s download site.

Both of writing shows that ‘PE6’ definition is Pin No.33.
I think pin 22 is SPI_2_MISO…?
I checked the pulse about pin 33 a few days ago.

But I will try pin 22 later!!

Great thanks!
devemin

11

I tried to use pin 22 for PWM.
But I could not.

I think pin 22 is SPI_2_MISO.

Anyway, In dts file,

adding <0xd 0 > at gpios,
removing <0xd > at gpio-input,
adding <0xd > at gpio-output-low.

modifing nvidia,function = “pwm2”; at “pe6{ }”

Connected oscilloscope to pin 22 and GND, no pulse.

I think my Nano is broken or the way of using PWM is very difficult lol.

I will wait for next JetPack information updating from NVIDIA official announcement.

thanks.
devemin

12

Hi devemin,

My apologizes, I think you are right. I didn’t checked pin 33 was defined as PE6.

I yes, It seems that something is missing to support PWM output on this JetPack.

Regards

13

PWM output issue is tracking at [url]What pins can be used for PWM control except 33 in samples - Jetson Nano - NVIDIA Developer Forums