The following links describe j21 header for tx1 and tx2 :
What is exactly j21 header ? Is this header for tx1/tx2 module or carrier ? Are these j21 pinout relevant for all carrier boards or is it only for a specific nvidia carrier board ?
I don’t understand why GPIOs number are different between tx1 and tx2. Isn’t there a pin compatability ?
This is on the development kit carrier board near the corner which is opposite to the module mounting point. Look for the 40-pin header there (basically in line with the buttons). Pin 1 has a small triangle printed in the mask and is right on the edge of the board closest to the buttons.
I understand where it is located.
But I don’t understand what it is.
Why for example, the gpios number are different for the same pins between tx1 and tx2 links in my post above ?
I can only speculate. Each generation of Tegra tends to add more of a given feature (e.g., GPIO ports, PCIe lanes, USB lanes, so on) by adding more controllers instead of modifying existing controllers. The GPIO numbering internal to the module is probably the same for the controller at some given base address when the base address matches across generations, but the routing of the pins is not hard wired…which pin of the module connects with which controller can differ (including if device tree differs). The pin on the module of a given number would be an exact match as to the pin on J21, but you can’t guarantee that GPIO internal to the module isn’t changed via software changing what controller is routed to. The number of module pins available does not change, but the content in the SoC needing to route to those pins does change.
I find strange thing in the spreadsheet from the link above:
I see that the hw gpio is different betweeb tx1 and tx2 for the same periopheral, for example:
uart1 tx in TX1 is hw pin U.00, while for TX2 is hw pin T.00
How can it be that the HW pin has changes for the same peripheral ?
Tegra pin HW GPIO
Jetson TX2 J21 GPIO Expansion Header Mapping
Tegra pin HW GPIO
I don’t know details, I’d only be guessing. But keep in mind many pins can be programmed to have different functions. It wouldn’t be unusual for example to be able to reverse +/- data lanes to accommodate a different hardware layout. This depends on the PINMUX/device tree. For this particular case I couldn’t tell you. Perhaps it is the same function, but from a different controller of the same type at a different base address.