Triaging from Software side states: Dump PADCTL_PEX_CTL_PEX_L*_CLKREQ_N_0 and PADCTL_PEX_CTL_PEX_L*_RST_N_0 pinmux values and check if settings are correct.
Would you like to elaborate on how to dump?
Triaging from Software side states: Dump PADCTL_PEX_CTL_PEX_L*_CLKREQ_N_0 and PADCTL_PEX_CTL_PEX_L*_RST_N_0 pinmux values and check if settings are correct.
Would you like to elaborate on how to dump?
Hi chairwa,
Are you using the devkit or custom board for AGX Orin?
What’s your Jetpack version in use?
Please refer to TRM document for the register.
For example,
PADCTL_PEX_CTL_PEX_L0_CLKREQ_N_0: 0x02437020
PADCTL_PEX_CTL_PEX_L0_RST_N_0: 0x02437028
You can run the following command to read their value.
$ sudo busybox devmem 0x02437020
$ sudo busybox devmem 0x02437028
Thanks for your reply.
It will be appreciated to add the similar information to above official web page .
I’m using official AGX orin devkit with jetson R35.4.1.
In Orin-TRM_DP10508002_v1.2p.pdf,
I can’t find PADCTL_PEX_CTL_PEX_L5 / PADCTL_PEX_CTL_PEX_L7 related offset.
I thinks it has mentioned to refer TRM for register address.
Which PCIe Controller are you using?
Have you tried to configure them from pinmux spreadsheet?
If so, could you share how you configure in pinmux spreadsheet?
OK. I found them: controller C5/C7, their names are
PADCTL_PEX_CTL_2_PEX_L5
PADCTL_PEX_CTL_3_PEX_L7
and in different section with PADCTL_PEX_CTL_PEX_L0.
Yes, L5 is in CTL2 and L7 is in CTL3.
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