Hi all — I’m working on a system where an Intel host is connected to a Jetson AGX Xavier that is configured as a PCIe Endpoint via a PCIe switch. I need to perform DMA transfers between the host and Jetson. Two approaches I’m considering:
A) Host programs Jetson DMA engine directly
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Expose the Jetson’s DMA engine registers in a BAR mapped to host memory space so the host can program DMA descriptors and kick the engine directly.
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Questions:
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Is it feasible to map Jetson PCIe EP internal registers (DMA engine) into a BAR visible to the host?
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What must the Jetson-side EP driver implement to support this (BAR setup, register window, cache / memory coherency considerations, MSI/MSI-X for interrupts)?
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Any caveats around IOMMU, address translation, or the PCIe switch (address routing / peer-to-peer limitations)?
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B) Jetson-controlled DMA (host sends command; Jetson initiates DMA)
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Host sends a command over a control BAR or side-band channel; Jetson software/driver performs the DMA to/from host memory.
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Questions:
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Typical control methods (MMIO command register, mailboxes, vendor-sideband channel, or a lightweight protocol over PCIe) to request Jetson to perform a DMA?
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Recommended kernel interfaces or existing driver examples for implementing the command/response and handing off DMA to the Jetson DMA engine (e.g., use of DMA APIs, scatter/gather, pinning host memory)?
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How to coordinate memory mapping from the host side so Jetson can access host buffers (IOMMU setup, mapping windows, and security)?
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Additional asks: sample EP driver snippets, kernel module examples, or references to Jetson-specific documentation would be appreciated.