Hi there!
I’m working on a system with an FPGA-based device and 2 Jetsons. Considering the JETSON 0 as RC of the PCIe architecture. It would be possible to do a Direct Memory Access (DMA) from FPGA to Jetson 1 (Endpoint)?
I would like to write a buffer data present in Jetson 1 with the FPGA writing the data through the PCIe communication, however, that pcie architecture has the Jetson 0 as Root Complex. Is there any issue in this architecture? Is the GPUDirect RDMA compatible with the Jetson configured as Endpoint?
I would like to have a pcie switch between there, is it a problem? The documentation isn’t clear about the switch compatibility.