Jetson Use-Case Question

Hi,

We arehinking of using the Jetson Xavier as PCIE root complex receiving data from an FPGA/PCIe endpoint over a x8 PCI Gen3, with no other CPU in the picture. Is that a feasible architecture?

Hi chintan.patel,

Please help to check below threads if can gain some ideas:
https://devtalk.nvidia.com/default/topic/1051650/jetson-agx-xavier/agx-xavier-pcie-real-read-performance-/
https://github.com/NVIDIA/jetson-rdma-picoevb

Thanks a lot. For the RDMA on the PICOEVB, it isn’t clear to me if the FPGA is the root complex and the Jetson endpoint, or vice versa. Can you clarify?

We arehinking of using the Jetson Xavier as PCIE root complex receiving data from an FPGA/PCIe endpoint over a x8 PCI Gen3, with no other CPU in the picture. Is that a feasible architecture?

Yes. Very much possible.
BTW, wondering how is your setup (or what you are planning to do) different from connecting a typical PCIe endpoint (like an NVMe device, NIC Etc…). Just to make sure that I’m not missing anything here.

Hi Vidyas,

I am new to GPUs, so I wasn’t sure if the typical configuration/use-case is having the Jetson/GPU be the PCIe endpoint with a CPU root complex (to essentially off-load computationally intensive tasks), or was it typical for the Jetson to be the only CPU/GPU in the system, and have a bunch of PCIe endpoints/peripherals connected to it. If the latter is typical, then you are right that the FPGA would just look like exactly like a more conventional PCIe endpoint (NIC card etc), to the Jetson.

Thanks
Chintan

Jetson AGX default configuration is to act as a system with PCIe root port so that any endpoint can be connected to it.
But it also has another personality where it can act like an endpoint so that it can be connected to another root port system (like an x86 system).