I am working on a project in which we are using NVIDIA AGX Xavier industrial SOM and a SBC with PCIE 4X slot. We want to communicate both using PCIE root complex and endpoint mode. The SBC would be running Linux. The plan is to configure the SBC as root complex and the NVIDIA AGX Xavier as the endpoint mode. I have searched the forum for any relevant tutorial but haven’t been able to find one. I just want to know is it possible to transfer data between these two SBC’s using PCIE. If yes, How can i implement this? Is there any tutorial available?
Secondly, how can i test the pcie endpoint mode on a NVIDIA AGX Xavier?
Thanks in advance
It is possible to configure AGX as a PCIe endpoint mode. There is support to emulate virtual ethernet connections on both RP and EP and have data transfer over the virtual ethernet interface. Please refer to https://developer.nvidia.com/embedded/dlc/jetson-agx-xavier-series-pcie-endpoint-design-guidelines-application-note
Thanks for the kind reply Vidyas.
We are using a NVIDIA AGX Xavier Industrial SOM with STEVIE™ Carrier for NVIDIA® AGX Xavier Module. We would be configuring the mentioned NVIDIA SOM as pcie endpoint. This carrier supports the following PCIE interfaces:-
5x PCIe Gen4 (16GT/s) Controllers
1x8, 1x4, 1x2, 2x1
PCIe Gen4, Root Port and Endpoint
Port: M.2 PCIe
The other end is a SBC with a x4 PCIE slot configured as root complex mode. We intend to use a M.2 to PCIE x4 adapter to connect both machines.
The guide you mentioned is related to the developer kit and the connections are mentioned for x8 PCIE configuration. Kindly guide us to configure the configuration mentioned in the guide for our setup i have mentioned above.
Secondly, kindly guide us what would be the considerations regarding the programming/code domain if we want to transfer data through pcie? Is the PCIe meant to be working as an emulation for the ethernet only?
I’m not sure about the mapping between the carrier’s ports and Tegra’s controller.
Since only Tegra’s C5 controller can operate in the endpoint mode, please use the port that maps to Tegra’s C5 controller.
Another important aspect is to have the REFCLK lanes (of the Host) routed to the input pins of the Tegra (Please refer to the reference schematics to understand this more) as the C5 controller in endpoint mode expects to receive the REFCLK from the host.
PCIe interface is not restricted to emulate only virtual ethernet connections. You can come up with your own way/protocol of transferring the data but we can’t really give any guidance on that. Please take a closer look at the virtual ethernet code and derive your own protocol/interface based on that. If you are looking for any specific aspects for which you couldn’t find answers in the virtual ethernet design/code, please let us know.
This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.