I want to add new /dev.spidev0.1 in the system on agx xavier, what should I do?

No, you can’t using dd to update the partition. The dtb need encrypt then write to the partition and also need remove the dtb from FDT line in the extlinux.conf

What should I do to make new dtb and jetson_io take effect at the same time?

need your help@ShaneCCC

Just replace the /boot/tegra194-p3668-all-p3509-0000-user-custom.dtb

another question, I follow this port https://orenbell.com/?p=436 to install rt-linux, I choose TARGET_RELEASE : 4.3, but rootfs/etc/nv_tegra_release REVISION Is 3.1, what’s problem?

Blockquote
yang@X280:~/Downloads/NVIDIA_file/agx_xavier_4.3$ source build/envsetup.sh
0. Jetson-Nano
1. Jetson-Xavier
2. Jetson-TX2
3. Jetson-TX1
Which device would you choose? [Jetson-Nano] 1
0. 4.1.1_DP
1. 4.2
2. 4.2.1
3. 4.2.2
4. 4.2.3
5. 4.3
Which release would you choose? [4.1.1_DP] 5
Login user of target device? [nvidia] nvidia
Login password of target device? [nvidia] 1
IP address of target device? 192.168.10.130

Please confirm below configuration:

TARGET_DEV : Jetson-Xavier
TARGET_RELEASE : 4.3
Target device login user : nvidia
Target device login password : 1
Target device IP : 192.168.10.130

Are these right? [n/y] y

C O M M A N D S:
rm_pwd: auth ssh connection without password
bspsetup: setup toolchain, kernel source
l4tout_setup: setup Xavier/Linux_for_Tegra
cbuild: build and install cboot
kmenuconfig: kernel menuconfig
kdefconfig: kernel defconfig
ksavedefconfig: update kernel defconfig
kbuild: build and install kernel image, dtb
kbuild -a: build and install kernel image, dtb, module
flash: flash image with options
flash_no_rootfs: flash all except rootfs
flash_cboot: flash cboot Image
flash_kernel: flash kernel Image

Hi CCC, I can use SPI communicate on agx board, but the Picture1 waveform I collected with the oscilloscope is not what I want. Picture 2 is the waveform I want. The same spidev_test program(8bit 12000000hz) is used and the parameters are the same. What should I change?

I noticed this port Jetson Xavier SPI Timing Characteristics, but I don’t know if it has anything to do with my problem, thanks

Picture1,continuous clock and CS pulse


Picture2,another board SPI,interval clock and CS pulse


SPI interval between two frames of data
image
image
image

Could you apply those changes from below link to try.

Hi CCC, I try your suggest, as below pic

but it did not solve my problem. My problem is the time interval between frame (not packet) and frame (8bit pulse), what needs to be set?

Blockquote
spi@3210000 {
status = “okay”;
spi@1 {
compatible = “spidev”;
reg = <0x1>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x11>;
nvidia,enable-hw-based-cs;
nvidia,clk-delay-between-packets;
};
};
spi@0 {
compatible = “spidev”;
reg = <0x0>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,rx-clk-tap-delay = <0x11>;
nvidia,enable-hw-based-cs;
nvidia,clk-delay-between-packets;
};
};
};

agx:


other(right scope):

The “nvidia,clk-delay-between-packets” may need using cs-gpios.

you once said in this post “You don’t need add “cs-gpios = <>” for these cs pins. The cs-gpios means you want to use any others gpio pin as cs. These two pin already configure as cs already.”

Sorry, I didn’t aware your are using “nvidia,clk-delay-between-packets” and you need to configure those pin as GPIO instead of SFIO pin.

How to get gpio num if using “nvidia,clk-delay-between-packets”?(I think its not use /sys/kernel/debug/tegra_pinctrl_…)

You can select any GPIO pin from the Xavier pin header to connect to the device cs and define it in the device tree.(cs-gpios=<>)

I use these patch now.( [0001-spi-tegra-fix-SPI-setup-and-hold-times.patch.txt]) , [0002-spi-tegra-optimize-delay-between-packets.patch.txt]
this is my device tree configuration, GPIO num reference “Jetson-Xavier-GPIO-mapping”, but still have problem. Please help to see if there is a problem with the configuration.

Blockquote
spi@3210000 {
status = “okay”;
spi@1 {
compatible = “spidev”;
reg = <0x1>;
spi-max-frequency = <33000000>;
cs-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(Q, 1) GPIO_ACTIVE_LOW>;
controller-data {
nvidia,rx-clk-tap-delay = <0x11>;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,clk-delay-between-packets = <0x5>;
};
};
spi@0 {
compatible = “spidev”;
reg = <0x0>;
spi-max-frequency = <33000000>;
cs-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(H, 0) GPIO_ACTIVE_LOW>;
controller-data {
nvidia,rx-clk-tap-delay = <0x11>;
nvidia,clk-delay-between-packets = <0x5>;
};
};
};

Could you file new topic and give proper header and much detail information then I can consult with nvidia developer.