I am exploring how the Factory+Flex Images work with innova2_flex_app. My current hypothesis is that the Factory Image (at 0x0) communicates with the ConnectX-5 to determine which configuration image, User or Flex, to load.
If you have a 1.8V Xilinx-compatible JTAG Adapter to recover from configuration failures or non-functional designs, you can ignore the Innova2 configuration system.
Add a Quad SPI IP Block to your designs and use XRT for configuration.
Include an M_AXI_LITE interface in your XDMA design:
Add a Quad SPI Block in Dual Quad Mode with 2 devices, a FIFO Depth of 256, and Use STARTUP Primitive Internal to IP:
Assign the block an address of 0x40000:
Connect usrcclkts to 0. The Block Diagram should look something like the following, plus the rest of your system.
Add the following to your project’s constraints .xdc file:
# Secondary Quad SPI Configuration Flash - Bank 65
# Primary Quad SPI Configuration Flash pins are single-purpose in STARTUPE3
set_property PACKAGE_PIN AM12 [get_ports spi_rtl_0_io0_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_0_io0_io]
set_property PACKAGE_PIN AN12 [get_ports spi_rtl_0_io1_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_0_io1_io]
set_property PACKAGE_PIN AR13 [get_ports spi_rtl_0_io2_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_0_io2_io]
set_property PACKAGE_PIN AR12 [get_ports spi_rtl_0_io3_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_0_io3_io]
set_property PACKAGE_PIN AV11 [get_ports spi_rtl_0_ss_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_0_ss_io]
# Differential System Clock - 100MHz - Bank 65
set_property PACKAGE_PIN AR14 [get_ports {sys_clk_100MHz_clk_p[0]}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {sys_clk_100MHz_clk_p[0]}]
After your project’s Synthesis+Implementation write your Memory Configuration File as an mcs file with a 0 Start Address. Use JTAG to initially write your configuration image to the Innova2.
Subsequently, the xbflash command can be used to program new bitstreams over existing ones.
lspci -d 10ee:
xbflash --card 3:00.0 --primary PROJECT_NAME_primary.mcs --secondary PROJECT_NAME_secondary.mcs
