Interlaced video out on HDMI?

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

Hi! We’re building an embedded system where our display requires interlaced video.

I’ve noticed that the fallback EDID (default_720p_edid in edid.c in the display driver) defines support for 720p, 1080i, 480p and 576p, but xrandr only lists the progressive formats as being available on HDMI-0 (ie, 720p, 480p and 476p are available, 1080i is not), and we cannot override that through xrandr addmode commands.

We replaced the fallback EDID with a custom EDID, that defined support for 480i, 480p, 576i, and 576p. With the custom EDID, only 480p and 576p formats were listed as available for HDMI-0, and again we couldn’t override to add the interlaced formats with xrandr addmode.

The Parker technical reference manual lists interlaced as being supported, CONFIG_TEGRA_DC_INTERLACE=y in our kernel config, and the t186_feature_entries_a found in nvdisp_config.c seem to indicate TEGRA_DC_FEATURE_FIELD_TYPE is supported for all 6 windows.

How can I enable interpolation? We need 480i and/or 576i for our system, and I haven’t seen anything in the documentation to say it isn’t supported.

2

The driver works only with predefined EDID modes. No interlaced mode is supported (sorry, you can’t do this without custom hardware to convert your interlaced to non-interlaced and updating EDID to show non-interlaced).

3

So to confirm, there is no hardware support for interlaced HDMI output, regardless of kernel flags like CONFIG_TEGRA_DC_INTERLACE and the Parker documentation?

There is no way for us to modify the video drivers to support this embedded use case, because there’s no hardware support for interlaced HDMI output?

4

There is no software support in the driver. I would guess that the hardware would not have a problem, but the driver will reject any mode which is either (a) not in the predefined mode pool (and no interlaced mode is in the pool), or (b) not presented via the EDID mechanism.

5

Thank you. Which file is the predefined mode pool located in, and what code and/or registers in the driver will we need to modify or support to get interlaced working? It’s an embedded device with only 1 display resolution, so we can afford ugly hacks if needed to get this working.

Unfortunately, we’ve already designed our electrical boards as we assumed from the documentation that interlaced was available. Revising our electrical boards will be problematic for us.

6

I haven’t edited a file directly for mode pool. You may find this thread of interest:
[url]https://devtalk.nvidia.com/default/topic/1031157/jetson-tx2/no-output-jetson-tx2-dev-board-connecting-to-an-external-5-quot-display/post/5246072/#5246072[/url]

And this specific reply:
[url]https://devtalk.nvidia.com/default/topic/1031157/jetson-tx2/no-output-jetson-tx2-dev-board-connecting-to-an-external-5-quot-display/post/5246072/#5246072[/url]

The above is basically about setting a mode (which is sort of related to the mode pool).

A much longer thread on the topic of mode pools and EDID can be found here:
[url]https://devtalk.nvidia.com/default/topic/1042546/reference-to-xorg-conf-and-resolution-settings/[/url]

Someone from NVIDIA will need to comment on whether it is possible to edit source code and pick a mode which is not within the mode pool (e.g., by adding the mode to the pool)…I am guessing this isn’t going to be possible (it is quite different to set a default mode from a pool than it is to get to the actual pool and edit pool content).