Iommu unhandled context fault during DMA transfer

I am attempting to configure an FPGA to DMA data via PCIe to memory on the Jetson TX2i.

I have allocated the destination memory using dma_zalloc_coherent. One of the arguments to dma_zalloc_coherent is the dma_handle, which I use to populate the destination address of the DMA descriptors.

Once the DMA is started, I see the following error appear in the dmesg output.
arm-smmu 12000000.iommu: Unhandled context fault: iova=0x00000000, fsynr=0x11, cb=22, sid=17(0x11 - AFI), pgd=0, pmd=0, pte=0

This is eventually followed up by some mc-err messages.

How do I decode the iommu message? Does the iova address tell me something?

arm-smmu 12000000.iommu: Unhandled context fault: iova=0x00000000, fsynr=0x11, cb=22, sid=17(0x11 - AFI), pgd=0, pmd=0, pte=0

add debug log to print source and destination iova address for DMA operation
as log clearly shows invalid 0 iova address (iova=0x00000000)

Below is a dump of the DMA descriptors. Note that there are 2 descriptors carrying 500kbytes each. The destination address is properly configured for the buffer allocated by dma_zalloc_coherent. The data is generated by an FPGA so I don’t believe the source address needs to be configured. The source address would be configured if I were DMA’ing from the Jetson to the FPGA.

[ 1355.140126] xdma:transfer_dump: xfer 0xffffffc19c84ee00, state 0x0, f 0x0, dir 2, len 0, last 0.
[ 1355.140130] xdma:transfer_dump: transfer 0xffffffc19c84ee00, desc 2, bus 0xfffc0000, adj 2.
[ 1355.140134] xdma:dump_desc: 0xffffff8010142000/0x00: 0xad4b0000 0xad4b0000 magic|extra_adjacent|control
[ 1355.140139] xdma:dump_desc: 0xffffff8010142004/0x04: 0x00080000 0x00080000 bytes
[ 1355.140142] xdma:dump_desc: 0xffffff8010142008/0x08: 0x00000000 0x00000000 src_addr_lo
[ 1355.140146] xdma:dump_desc: 0xffffff801014200c/0x0c: 0x00000000 0x00000000 src_addr_hi
[ 1355.140149] xdma:dump_desc: 0xffffff8010142010/0x00: 0xffe00000 0xffe00000 dst_addr_lo
[ 1355.140153] xdma:dump_desc: 0xffffff8010142014/0x04: 0x00000000 0x00000000 dst_addr_hi
[ 1355.140156] xdma:dump_desc: 0xffffff8010142018/0x08: 0xfffc0020 0xfffc0020 next_addr
[ 1355.140159] xdma:dump_desc: 0xffffff801014201c/0x0c: 0x00000000 0x00000000 next_addr_pad
[ 1355.140162] xdma:dump_desc:
[ 1355.140166] xdma:dump_desc: 0xffffff8010142020/0x00: 0xad4b0012 0xad4b0012 magic|extra_adjacent|control
[ 1355.140169] xdma:dump_desc: 0xffffff8010142024/0x04: 0x00080000 0x00080000 bytes
[ 1355.140172] xdma:dump_desc: 0xffffff8010142028/0x08: 0x00000000 0x00000000 src_addr_lo
[ 1355.140176] xdma:dump_desc: 0xffffff801014202c/0x0c: 0x00000000 0x00000000 src_addr_hi
[ 1355.140179] xdma:dump_desc: 0xffffff8010142030/0x00: 0xffe80000 0xffe80000 dst_addr_lo
[ 1355.140183] xdma:dump_desc: 0xffffff8010142034/0x04: 0x00000000 0x00000000 dst_addr_hi
[ 1355.140186] xdma:dump_desc: 0xffffff8010142038/0x08: 0xfffc0000 0xfffc0000 next_addr
[ 1355.140190] xdma:dump_desc: 0xffffff801014203c/0x0c: 0x00000000 0x00000000 next_addr_pad

Could this be an issue with the MSI interrupt? Is the MSI interrupt potentially causing a read/write to address 0x0?

For any DMA operation both source and destination address should be valid. Please try to program source address as well.

Please try to program source address as well.

I have a similar problem.
What does the program source address mean?

DMA transactions have a source and destination address. In my case, I am interfacing with a Xilinx XDMA module. This module sets up a scatter/gather DMA transaction. For our app, we are moving data from the FPGA to the Jetson. The destination address was set to a buffer allocated using dma_alloc_coherent.

Originally, I was not setting the source address. Since the data was being generated by the FPGA, I didn’t know what to put for the source address. It turns out the Xilinx XDMA module uses the source address to find the next DMA transfer to perform. It is their way to setup a linked list of DMA transfers.

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