Is Jetson Orin RGMII interface support MAC to MAC?

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
1

As the title says. Is Jetson Orin RGMII interface support MAC to MAC ?

Now, i want to connet the RGMII interface to a switch chip yt9215rb.

I modify the device tree (tegra234-p3737-0000+p3701-0000.dts) as following

ethernet@6800000 {
status = "disabled";
phy-handle = <&mgbe0_phy>;
phy-mode = "10gbase-r";
mdio {
    #address-cells = <1>;
    #size-cells = <0>;

mgbe0_phy: phy@0 {
        compatible = "ethernet-phy-ieee802.3-c45";
        reg = <0x0>;
        #phy-cells = <0>;
    };
};
};// Enable RGMII Gigabit

ethernet@2310000 {
status = "okay";
/* 1. Set the physical interface mode to RGMII */
/* Note: Use “rgmii-id”, “rgmii-rxid”, “rgmii-txid”, or “rgmii”
depending on where the clock delays are added on your custom board \*/
phy-mode = "rgmii-id"; 
nvidia,mac-addr-idx = <0>;
nvidia,skip_mac_reset = <1>;
// nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;
/* 2. Remove standard PHY references (if they exist in an included dtsi) */
/delete-property/ phy-handle;
/delete-node/ mdio; /\* Ensure MDIO node is not initialized \*/
/* 3. Define the fixed link to your auto-configured switch */
fixed-link {
    speed = <1000>;      /\* RGMII operates at 1000 Mbps (1 Gbps) \*/
    full-duplex;         /\* Standard for switch-to-MAC connections \*/
};
};
  1. modify p3701.conf.common as following

#ODMDATA=“gbe-uphy-config-22,hsstp-lane-map-3,nvhs-uphy-config-0,hsio-uphy-config-0,gbe0-enable-10g”;
ODMDATA=“gbe-uphy-config-0,hsstp-lane-map-3,nvhs-uphy-config-0,hsio-uphy-config-0”;

  1. pinmux configuration and generate dtsi
        eqos_txc_pe0 {
            nvidia,pins = "eqos_txc_pe0";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
        };
eqos_td0_pe1 {
            nvidia,pins = "eqos_td0_pe1";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
        };
eqos_td1_pe2 {
            nvidia,pins = "eqos_td1_pe2";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
        };
eqos_td2_pe3 {
            nvidia,pins = "eqos_td2_pe3";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
        };
eqos_td3_pe4 {
            nvidia,pins = "eqos_td3_pe4";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
        };
eqos_tx_ctl_pe5 {
            nvidia,pins = "eqos_tx_ctl_pe5";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
        };
eqos_rd0_pe6 {
            nvidia,pins = "eqos_rd0_pe6";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_ENABLE>;
            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
        };
eqos_rd1_pe7 {
            nvidia,pins = "eqos_rd1_pe7";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_ENABLE>;
            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
        };
eqos_rd2_pf0 {
            nvidia,pins = "eqos_rd2_pf0";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_ENABLE>;
            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
        };
eqos_rd3_pf1 {
            nvidia,pins = "eqos_rd3_pf1";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_ENABLE>;
            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
        };
eqos_rx_ctl_pf2 {
            nvidia,pins = "eqos_rx_ctl_pf2";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_ENABLE>;
            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
        };
eqos_rxc_pf3 {
            nvidia,pins = "eqos_rxc_pf3";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_ENABLE>;
            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
        };
eqos_sma_mdio_pf4 {
            nvidia,pins = "eqos_sma_mdio_pf4";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
        };
eqos_sma_mdc_pf5 {
            nvidia,pins = "eqos_sma_mdc_pf5";
            nvidia,function = "eqos";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
        };

and gpio dtsi as following

    gpio_main_default: default {
        gpio-input = <TEGRA234_MAIN_GPIO(B, 0)
        TEGRA234_MAIN_GPIO(Y, 3)
        TEGRA234_MAIN_GPIO(Y, 7)
        TEGRA234_MAIN_GPIO(Z, 1)
        TEGRA234_MAIN_GPIO(Z, 3)
        TEGRA234_MAIN_GPIO(Z, 4)
        TEGRA234_MAIN_GPIO(Z, 5)
        TEGRA234_MAIN_GPIO(Z, 6)
        TEGRA234_MAIN_GPIO(Z, 7)
        TEGRA234_MAIN_GPIO(P, 4)
        TEGRA234_MAIN_GPIO(P, 6)
        TEGRA234_MAIN_GPIO(Q, 6)
        TEGRA234_MAIN_GPIO(Q, 7)
        TEGRA234_MAIN_GPIO(R, 1)
        TEGRA234_MAIN_GPIO(N, 4)
        TEGRA234_MAIN_GPIO(N, 1)
        TEGRA234_MAIN_GPIO(G, 0)
        TEGRA234_MAIN_GPIO(G, 1)
        TEGRA234_MAIN_GPIO(G, 2)
        /*TEGRA234_MAIN_GPIO(G, 4)*/ /* EQOS Interrupt */
        TEGRA234_MAIN_GPIO(G, 7)
        TEGRA234_MAIN_GPIO(H, 0)
        TEGRA234_MAIN_GPIO(H, 5)
        TEGRA234_MAIN_GPIO(H, 7)
        TEGRA234_MAIN_GPIO(I, 0)
        TEGRA234_MAIN_GPIO(I, 1)
        TEGRA234_MAIN_GPIO(I, 2)
        TEGRA234_MAIN_GPIO(AC, 3)
        TEGRA234_MAIN_GPIO(AC, 4)
        TEGRA234_MAIN_GPIO(AC, 5)
        TEGRA234_MAIN_GPIO(K, 0)
        TEGRA234_MAIN_GPIO(K, 1)
        TEGRA234_MAIN_GPIO(K, 6)
        TEGRA234_MAIN_GPIO(K, 7)
        TEGRA234_MAIN_GPIO(L, 2)
        TEGRA234_MAIN_GPIO(L, 3)
        TEGRA234_MAIN_GPIO(AG, 0)
        TEGRA234_MAIN_GPIO(AG, 1)
        TEGRA234_MAIN_GPIO(AG, 2)
        TEGRA234_MAIN_GPIO(AG, 3)
        TEGRA234_MAIN_GPIO(AG, 6)
        TEGRA234_MAIN_GPIO(AG, 7)
        TEGRA234_MAIN_GPIO(AF, 2)
        TEGRA234_MAIN_GPIO(AF, 3)
                    >;
        gpio-output-low = <
        TEGRA234_MAIN_GPIO(X, 0)
        TEGRA234_MAIN_GPIO(X, 1)
        TEGRA234_MAIN_GPIO(Z, 2)
        TEGRA234_MAIN_GPIO(N, 3)
        TEGRA234_MAIN_GPIO(H, 1)
        TEGRA234_MAIN_GPIO(H, 3)
        TEGRA234_MAIN_GPIO(H, 4)
        TEGRA234_MAIN_GPIO(H, 6)
        TEGRA234_MAIN_GPIO(I, 5)
        TEGRA234_MAIN_GPIO(AC, 0)
        TEGRA234_MAIN_GPIO(AC, 1)
        TEGRA234_MAIN_GPIO(AC, 2)
        TEGRA234_MAIN_GPIO(A, 1)
        TEGRA234_MAIN_GPIO(A, 2)
                    >;

        gpio-output-high = <
        TEGRA234_MAIN_GPIO(Y, 0)
        TEGRA234_MAIN_GPIO(Y, 1)
        TEGRA234_MAIN_GPIO(Y, 2)
        TEGRA234_MAIN_GPIO(Y, 4)
        TEGRA234_MAIN_GPIO(Z, 0)
        TEGRA234_MAIN_GPIO(Q, 1)
        TEGRA234_MAIN_GPIO(G, 3)
        TEGRA234_MAIN_GPIO(G, 5) /* EQOS reset */
        TEGRA234_MAIN_GPIO(AC, 7)
        TEGRA234_MAIN_GPIO(K, 4)
        TEGRA234_MAIN_GPIO(K, 5)
        TEGRA234_MAIN_GPIO(AG, 4)
        TEGRA234_MAIN_GPIO(AG, 5)
        TEGRA234_MAIN_GPIO(A, 0)
        TEGRA234_MAIN_GPIO(A, 3)
                    >;
    };

};

gpio@c2f0000 {
    gpio-init-names = "default";
    gpio-init-0 = <&gpio_aon_default>;
gpio_aon_default: default {
        gpio-input = <
        TEGRA234_AON_GPIO(EE, 5)
        TEGRA234_AON_GPIO(EE, 6)
        TEGRA234_AON_GPIO(EE, 2)
        TEGRA234_AON_GPIO(EE, 4)
        TEGRA234_AON_GPIO(CC, 0)
        TEGRA234_AON_GPIO(CC, 1)
        TEGRA234_AON_GPIO(AA, 0)
        TEGRA234_AON_GPIO(AA, 1)
        TEGRA234_AON_GPIO(AA, 2)
        TEGRA234_AON_GPIO(AA, 3)
        TEGRA234_AON_GPIO(AA, 7)
        TEGRA234_AON_GPIO(BB, 0)
        TEGRA234_AON_GPIO(BB, 1)
        TEGRA234_AON_GPIO(BB, 2)
                    >;
        gpio-output-low = <
        TEGRA234_AON_GPIO(CC, 2)
        TEGRA234_AON_GPIO(CC, 3)
        TEGRA234_AON_GPIO(AA, 4)
                    >;

        gpio-output-high = <
        TEGRA234_AON_GPIO(BB, 3)
                    >;
    };

};

gpio@9250000 {
    gpio-init-names = "default";
    gpio-init-0 = <&gpio_fsi_default>;
gpio_fsi_default: default {
        gpio-input = <
                    >;
        gpio-output-low = <
            >;
        gpio-output-high = <
            >;
    };
};

build and flash, i got the following dmesg

[ 10.373714] nvethernet 2310000.ethernet: Adding to iommu group 50
[ 10.375893] nvethernet 2310000.ethernet: failed to read skip mac reset flag, default 0
[ 10.375899] nvethernet 2310000.ethernet: failed to read MDIO address
[ 10.375903] nvethernet 2310000.ethernet: Failed to read nvida,pause_frames, so setting to default support as disable
[ 10.375906] nvethernet 2310000.ethernet: setting to default DMA bit mask
[ 10.375915] nvethernet 2310000.ethernet: max-platform-mtu DT entry missing, setting default 1500
[ 10.386075] platform 13800000.display:nvdisplay-niso: Adding to iommu group 51
[ 10.396880] nvethernet 2310000.ethernet: Ethernet MAC address: 3c:6d:66:11:32:cf
[ 10.415145] spi-tegra114 3230000.spi: Adding to iommu group 1
[ 10.439394] tegra-hda 3510000.hda: Adding to iommu group 52
[ 10.441617] -->macsec_probe()
[ 10.441652] nvethernet 2310000.ethernet: macsec parameter is missing or disabled
[ 10.441655] <–macsec_probe()
[ 10.441657] nvethernet 2310000.ethernet: Macsec not supported/Not enabled
[ 10.452855] nvethernet 2310000.ethernet: eth0 (HW ver: 53) created with 8 DMA channels
…
[ 14.309078] nvethernet 2310000.ethernet: [poll_check][42][type:0x4][loga-0x0] poll_check: timeout
[ 14.309088] nvethernet 2310000.ethernet: ether_open: failed to initialize MAC HW core with reason -1
…

someone have the simillar problem?

2

*** Please note that this reply is generated by LLM automatically ***

The question is asking if the Jetson AGX Orin’s RGMII interface supports MAC to MAC connection, and if it can be connected to a switch chip yt9215rb.

The RGMII (Reduced Gigabit Media Independent Interface) is a variant of the GMII (Gigabit Media Independent Interface) that is used to connect Ethernet MACs to PHYs (Physical Layer devices). The RGMII interface is a reduced version of the GMII, with fewer pins and a lower clock rate.

The Jetson AGX Orin’s RGMII interface is supported by the device tree, as shown in the provided code snippet. The device tree configuration sets the physical interface mode to RGMII and defines the fixed link to the autoconfigured switch.

However, the provided dmesg output shows several errors and warnings related to the Ethernet MAC and PHY configuration. Specifically, the output shows that the MAC address is not properly set, and the MDIO address is not readable. Additionally, the output shows that the MACsec (Media Access Control Security) is not supported or enabled.

To resolve these issues, you may need to modify the device tree configuration to properly set the MAC address and MDIO address. You may also need to enable MACsec support in the device tree configuration.

In terms of connecting the RGMII interface to a switch chip yt9215rb, it is possible to do so, but it requires proper configuration of the device tree and the switch chip. The yt9215rb switch chip is a 5-port Gigabit Ethernet switch that supports RGMII and other interfaces. To connect the Jetson AGX Orin’s RGMII interface to the yt9215rb switch chip, you will need to configure the device tree to properly set the RGMII interface mode and the switch chip configuration.

In comparison to other Jetson modules, the Jetson AGX Orin’s RGMII interface is similar to the RGMII interface on other Jetson modules, such as the Jetson Orin NX and Jetson Orin Nano. However, the specific device tree configuration and switch chip configuration may vary depending on the module and the use case.

In summary, the Jetson AGX Orin’s RGMII interface supports MAC to MAC connection, and it can be connected to a switch chip yt9215rb with proper configuration of the device tree and the switch chip. However, the provided dmesg output shows several errors and warnings related to the Ethernet MAC and PHY configuration, which need to be resolved to properly configure the RGMII interface.

Here are some recommendations to resolve the issues:

  1. Modify the device tree configuration to properly set the MAC address and MDIO address.
  2. Enable MACsec support in the device tree configuration.
  3. Configure the switch chip yt9215rb to properly set the RGMII interface mode and the switch chip configuration.
  4. Verify the device tree configuration and the switch chip configuration to ensure that they are properly set up.

By following these recommendations, you should be able to resolve the issues and properly configure the RGMII interface on the Jetson AGX Orin.

*** Please give the thumbs up if you get answers you like. Or provide feedback to help us improve the answer. ***

3

yt9215rb will auto configured self by the external eeprom. so AGX Orin should not reset it, it just communicate to yt9215rb directly by mac to mac.

5

update.

now AGX Orin can connect to yt9215rb correctly. both txc and rxc can checked out 125MHz wave.

ifconfig can list the eth0 correctly. but AGX Orin cannot ping the laptop in the same local network, vice versa.

How AGX Orin tune the tx delay and rx delay on RGMII interface?

6

I am also interested in this feature. I found this information in the Jetson AGX Orin datasheet:

image
image827×1188 112 KB

image
image825×716 60 KB

I don’t know if this matters, but the MDIO pin needs a pull-up resistor. With a MAC-to-MAC connection (no PHY), I’m not sure if the MDIO interface is used at all.

I also see here that there is a note saying that “NVIDIA Orin SoC does not support RGMII-ID feature, meaning that Orin RGMII TX CLK and DATA are edge aligned, while Orin RGMII RX CLK and DATA must be center aligned. Therefore, a CLK-to-DATA skew of greater than 1.5ns and less than 2.0ns must be ensured on Orin RGMII RX signals, either via MAC/PHY RGMII-ID or via PCB trace delay.”

My interpretation of this note is that the Orin MAC does not support RGMII internal delay at all. I think the link peer (the yt9215rb device connected to the Orin you are trying to ping) needs to implement internal delay on both the TX and the RX path.

In your update you said that the AGX Orin can connect. Did you make any changes to the configuration in your first post? If so, could you please share?

7

of cource. i use AGX Orin 64G module. and i modify all the files base on jetson-agx-orin-devkit.conf. the update is i found out i modify the wrong pinmux dtsi.

the right dtsi files is

Linux_for_Tegra/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi

and

Linux_for_Tegra/bootloader/tegra234-mb1-bct-gpio-p3701-0000.dtsi.

i modify the wrong pinmux dtsi file tegra234-mb1-bct-pinmux-p3701-0000.dtsi . so after i fix this point, the dmesg show the eth0 link up. and ifconfig will list the eth0 interface.

1 Like
8

Thank you for sharing! I think the reason that ping fails is that RGMII internal delay needs to be handled by the device that the AGX Orin is connected to (as explained above). This delay should be 1.5ns to 2ns according to the datasheet, and there is no way for the Orin MAC to be able to implement this delay. Maybe your yt9215rb is able to be configured so that handles the internal delay on both the transmit and receive datapaths so that ping will work. Please post again if this was the solution so that we can help others in the future who may also have this question.

9

I think you are absolutely right! because, i have test add 2ns txc delay on switch side. Then, the ping worked, but not worked fine. some icmp packet will be captured by wireshark, but some not.

so, I will add some rxc delay on switch side. i think your suggestion will be useful. I will be back to share my work.

10

@scarrion I think the problem has been resolved. in switch(yt9215) side, add 1ns RXC delay and add 2ns TXC delay. Then ping worked find.

so, if you want to use the RGMII interface of AGX Orin, you should make sure that the phy or switch chip has the function of tunning the txc delay and rxc delay simmultaneously.

but i still feeling that the AGX Orin’s RGMII interface can tune the TXC delay, but nvidia didnot open that or i didnot found the method to add txc delay?? can someone tell me?

1 Like
11

@sddzycnq I could not find any documentation anywhere that explains if it is possible to configure RGMII internal delay on the Jetson Orin. I only found the application note that I referenced in my other post above. That footnote that says “NVIDIA Orin SoC does not support RGMII-ID feature” makes me think that this is not possible, but I’m not certain.

1 Like