J509 Camera Connector SPI Pin Mapping Question

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
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1

Hi,

I am referring to both P3737_A05 concept schematics and base version downloaded from Jetson Download Center while designing a camera board that connects to J509 on Jetson AGX Orin 64GB developer kit module.

In the schematic, I noticed that J509 pins 111 (SCK), 112 (MOSI), 113 (CS0), and 114 (MISO) are labeled as CAM_SPI signals. However, in the Jetson AGX Orin Developer Kit Carrier Board Specification, these same pins are marked as unused, while pins 103, 104, 106, and 117 are identified as SPI signals.

Could you please clarify which SPI pin mapping should be used for a custom GMSL deserializer design connected to J509?

Thank you for your help.

4

For the SPI2 signals listed in the carrier-board specification, Table 3-1 gives:

J509 pin Signal Module pin

━━━━━ ━━━━━ ━━━━━━

117 SPI2_CLK E61

──── ────── ───────

103 SPI2_MOSI F60

─── ────── ───────

106 SPI2_MISO D62

─── ────── ─────

104 SPI2_CS0_N D60

These signals are 1.8 V and are described as camera-interrupt GPIOs in the default configuration. Using them for SPI requires the

corresponding pinmux and controller/device-tree configuration. Carrier-board specification (https://developer.nvidia.com/assets/embedded/

secure/jetson/agx_orin/jetson_agx_orin_devkit_carrier_board_specification_sp)

The CAM_SPI signals on J509 pins 111–114 are an optional route. NVIDIA previously confirmed that this route connects to SPI1 through

normally unpopulated zero-ohm resistors R413–R416, requiring board rework. This explains why schematic signal names can exist while the

connector specification marks those pins unused. Earlier NVIDIA clarification (https://forums.developer.nvidia.com/t/j509-camera-

connector-pin-configuration/265815/9)

For a camera board intended to work with an unmodified developer-kit carrier, use the documented SPI2 group above. If you intend to use

CAM_SPI instead, first confirm the resistor population and routing against your exact P3737-A05 schematic, BOM, and physical carrier

revision; the earlier resistor guidance should be checked before applying it to A05.

Please also ensure the deserializer-side SPI voltage matches the connector’s electrical levels.