[Jetson AGX Orin 32 R35.5.0] How to modify the maximum number of MSIs supported by AGX Orin

[WayneWWW]

GIC MSI is disabled in rel-36 because some upstream code review rejection.

Please refer to this topic if you want GIC MSI.

R36.3 Patch to re-enable GICv2m for PCIe MSI interrupts and restore I/O performance

R36.x has a major performance regression over R35.x. The problem is all PCIe MSI interrupts are now routed to CPU 0 whereas they used to be distributed across all CPU cores. For any workload requiring high I/O bandwidth, e.g. multiple NVME devices, this results in lower performance and system lock ups due to CPU 0 being overwhelmed with interrupts. There was an earlier thread on this issue but with no solution: [Orin NX R36.2 cannot change IRQ smp affinity - #7 by thegtx25] I’ve ported the o…