[Jetson AGX Orin 32 R35.5.0] How to modify the maximum number of MSIs supported by AGX Orin

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
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1

The L4T documentation describes how to increase the number of PCIE MSIs, but I cannot find the corresponding file in the L4T source code.

By the way, the problem I am currently encountering is that in our custom Orin carrier board, there is a PCIe switch connected to Orin, with four SSDs mounted on the PCIe switch; there is also an FPGA connected to Orin. When I start the system, lspci can see all the devices, but the driver corresponding to the FPGA prints the following when requesting an MSI interrupt from the kernel

[   14.269797] xdma:enable_msi_msix: pci_enable_msi()
[   14.269972] xdma:enable_msi_msix: Couldn't enable MSI mode: -28

So I suspect that the number of msi interrupts opened by L4T is insufficient.
The version of Jetpack I am using is 5.1.3.

3

file is in hardware/nvidia/soc/t23x/kernel-include/dt-bindings/interrupt-controller/tegra-t23x-agic.h.

4

Thank you, I understand. it·s work

By the way, in Jetpack 6.2–L4T 36.4.3, is there a maximum number of interrupts for msi, and how can it be changed?

5

GIC MSI is disabled in rel-36 because some upstream code review rejection.

Please refer to this topic if you want GIC MSI.

6

Thanks!

8

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