Jetson AGX Orin 64Gb: Matching lanes in CSI interface

[dmitry.leonov]

Hello,
I am developing some test card to interface with Jetson AGX Orin 64Gb dev kit for camera checking.
For matching line along the entire route, I want to know if CSI lanes in x2 and x4 configuration are matched (Trace Delay Skew between DQ and CLK) in Orin platform?

Unfortunately, I didn’t find any information about nets status.

Thanks for answer.

[Trumany]

I dont get what you mean. But if you mean test on devkit, you can refer to the sch/pcb files of devkit carrier in DLC.

Jetson AGX Orin Series Developer Kit Carrier Board Design Files

[dmitry.leonov]

Hello Trumany,
Thanks for the answer.
Lanes in CSI interface must be matched (per MIPI CSI D-PHY Requirements).
And I want to be sure that the current lanes are matched inside Jetson AGX Orin 64Gb dev kit because I will be adding some test card between Jetson AGX Orin dev kit and Camera (without cables).
Unfortunately, Nvidia didn’t published ORIN SOM layout or some net’s status so layout of carrier card not helping me so much.

I believe that these lanes are matched inside the dev kit, I’m just making sure it’s true.

Thanks and BR,
Dima

[Trumany]

You can refer to below info in devkit carrier board specification for the usage/lane mapping of the camera expansion connector. It is not single option only. BTW, generally, you can find necessary docs in DLC.

Jetson AGX Orin Developer Kit Carrier Board Specification

3.2 Camera Expansion Connector
The Jetson AGX Orin carrier board includes a 120-pin (2 × 60, 0.5 mm pitch) camera expansion connector (J509). The connector used on the carrier board is a Samtec QSH-060-01-H-D-A. The mating connector is a Samtec QTH-060-0x-H-D-A (x is for the height).
The expansion connector includes interface options for multiple CSI DPHY or CPHY cameras. Refer to the Jetson AGX Orin Camera Module Hardware Design Guide for more information.
 CSI up to 4 × 4 lane or 6 × 2 lane
 CAM_I2C, Clock and Control GPIOs for the cameras
 I2C (2x in addition to CAM_I2C)

[dmitry.leonov]

Trumany,
I meant if CSI lanes are matched inside Jetson AGX Orin Dev kit by length as per requirements:

Thank you.

[Trumany]

Yes. And these requirements are for custom carrier board design based on module inside routing.

[dmitry.leonov]

Thank you Trumany for support.

Regards,
Dima