MIPI CSI-2 six camera (4-lane, 4-lane, 4-lane, 1-lane, 1-lane, 1-lane) signal allocation


I am looking to design a PCB for the Jetson AGX Orin which splits the MIPI CSI-2 into the following six camera interfaces:

  • Camera1 4-lanes
  • Camera2 4-lanes
  • Camera3 4-lanes
  • Camera4 1-lane
  • Camera5 1-lane
  • Camera6 1-lane

Is this a viable without additional hardware? If so, how should the eight CSI clocks be allocated or am I completely free to choose?

Many thanks in advance.

Your lane mapping is not supported. Please refer to the Orin Design Guide doc in DLC for CSI design.

Hi Trumany,

Many thanks for your response.

I looked through the Orin Design Guide but am having trouble understanding why this option is not possible, is it because a 1-lane solution always occupies 2-lanes? With this in mind, would the following two solutions be valid?

Solution1 - 5 Cameras
Camera1 4-lanes
Camera2 4-lanes
Camera3 4-lanes
Camera4 1-lane
Camera5 1-lane

Solution2- 6 Cameras
Camera1 4-lanes
Camera2 3-lanes
Camera3 3-lanes
Camera4 1-lane
Camera5 1-lane
Camera6 1-lane

Many thanks.

The DG has given the detail info on this. The supported lane mapping should follow below table, and same lane should not be used for x2 and x4 at same time. For example, your solution 1 is supported, while not for solution 2.

Hi Trumany,

Thanks again for your explanation.

One thing I still cant understand is why in table 10-4 (below), a 3-lane camera and a 1-lane camera can coexist and yet my solution2 is not valid. Is this a feature of C-PHY? FYI we will be using D-PHY cameras.

CPHY is different to DPHY.

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