CSI-2 layout lanes lengths on AGX Orin Developer kit (J509 connector)


I would like to make one board which will be connected to Jetson Orin AGX developer kit through J509 connector. In the documentation, I have only found maximum allowed length of CSI-2 bus in layout depending on the maximum required speed. Are CSI-2 lanes lengths on the developer kit side equlizied so that I only have to take care of ii on my board side, or they have different lengths on developer kit side? In case they are different on developer kit side, where can I find those data? Thank you in advance!

Best regards,
Nikola Balaban

Hi, you can get the devkit CSI trace length in Xavier carrier board spec doc in DLC.

Hello, thank you for your fast response. I assume you mean on the “Table 3-2 Camera Module CSI PCB Trace allowances - D-PHY” in the document (since D-PHY is of my interest). There are given a) the maximum delay on the carrier board (Dev. kit) and b) maximum allowed delays for the whole trace (Dev. kit + my custom board). Is this maximum delay on the carrier board (360 ps) equal for all traces on the dev kit or it is just for the one lane with the greatest delay? If it is for one, I would like to compensate on my board so that all have the same delay. For that I would need either delay or absolute length of each trace/lane. Is that available? Thank you.

You can use the max trace length request in Design Guide to reduce the trace length of devkit carrier to get the trace length that can be used on your custom design.

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