Hardware design Trace Impedance about Diff pair / Single Ended control?

1:I want to design my Carry Board to fit TX2, but when I read “Jetson_TX2_OEM_Product_DesignGuide”,I found that the MIPI-CSI-2 “Impedance about Diff pair / Single Ended” is 90 / 45-55Ω.
When I read other design guide about MIPI CSI-2 100 / 50Ω 10%.
Whitch one should I use to my design.

2:when I read “Jetson_TX2_OEM_Product_DesignGuide”, it says “Max Trace Delay” about MIPI CSI-2 is 186 (1100ps)mm.If I want to use the MIPI CSI-2 the trace more than 186mm, what should I do,I need to use MIPI CSI-2 trace(include cable)about 1000mm,I consider use Buffer/ReDriver , does this workable?


  1. 90/45-55 is ok, as it has +/- 10% tolerance available.

  2. The maximum lane flight time is defined at 2ns in MIPI specification, so the 1100ps in OEM DG is must, i don’t think a buffer is workable, this 1100ps should include all your PCBs’ and device’s routing.

thank for your answer.

  1. Where can I find The maximum lane flight time?i don’t have the MIPI specification standard,and i don’t have the right to download in that MIPI Alliance web .
  2. My project need the tx2 to connect the camera,the cable is about 1000mm(),so in the Phy,MIPI CSI-2 don’t fit direct to use. I should transfer the MIPI CSI-2 Phy to other format?
  1. You can also google that, here is for your reference: http://www.analog.com/media/en/technical-documentation/application-notes/AN-1337.pdf

  2. Yes, 1000mm is too much longer than that in specification.

Thanks a lot.I got it.