In Table 35 of the Jetson TX2/TX2i OEM Product Design Guide, the MIPI CSI and DSI signal routing requirements are listed. I have a few questions:
At the 2.5Gbps line rate for MIPI, I see the maximum trace delay is listed as 350 mm (ps). Is this a maximum trace length of 350mm? Or 350 ps and assuming a propagation delay of 150ps/in in regular FR-4? Seems like it is the former and the ps value was never populated in this table.
The “Max Trace Delay Skew between DQ & CLK” I assume refers to the skew between MIPI clock and data lanes, as MIPI is a source-synchronous interface. The majority of literature and devices I can find have not confirmed for me what the actual allowable skew between clock and data is. Is this saying that even with the MIPI calibration that takes place in NVCSI, at the highest line rate I can’t have more than 5ps of skew between CLK and any DATA pair?
We are hoping to use several signal switches in our application for signal routing; these are all very high-bandwidth switches designed for either PCIe 3.0 or DisplayPort applications with a 7GHz or better bandwidth. However, these switches are intended to pass 4 data lines of traffic, not 5. If I route my MIPI clock or some data lane through another switch, and I only truly have 5ps of clock and data skew, there is absolutely no way I can meet that specification when factoring in PVT variations.
Some older devices that are 1.5Gbps parts report skew numbers in the 10s to 20s of ps range on their datasheet for inter-pair skew. Other newer devices, like the TS5MP646 intended for 2.5Gbps MIPI switching applications offer a 1ps typical intra-pair skew and 4ps inter-pair skew number.
I am surprised at the number of setups that “seem” to work with long (relatively speaking) harnessing (I-PEX CABLINE micro-coax) and multiple connectors; if all parties involved are truly splitting these specified margins between each PCB and harness, the traces must literally be routed with tolerances on the order of 10s of micrometers on length. Coupled with the fact that NVIDIA uses 90 ohms for their MIPI routing recommendation to optimize SI for their package / device while my camera vendor may have utilized 100 ohms and my harnessing is 100 ohms, I have no idea how this stuff is seemingly working with the published design margins at the published top speeds.