MIPI CSI-2 Clock/Data Skew

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

In Table 35 of the Jetson TX2/TX2i OEM Product Design Guide, the MIPI CSI and DSI signal routing requirements are listed. I have a few questions:

  1. At the 2.5Gbps line rate for MIPI, I see the maximum trace delay is listed as 350 mm (ps). Is this a maximum trace length of 350mm? Or 350 ps and assuming a propagation delay of 150ps/in in regular FR-4? Seems like it is the former and the ps value was never populated in this table.

  2. The “Max Trace Delay Skew between DQ & CLK” I assume refers to the skew between MIPI clock and data lanes, as MIPI is a source-synchronous interface. The majority of literature and devices I can find have not confirmed for me what the actual allowable skew between clock and data is. Is this saying that even with the MIPI calibration that takes place in NVCSI, at the highest line rate I can’t have more than 5ps of skew between CLK and any DATA pair?

We are hoping to use several signal switches in our application for signal routing; these are all very high-bandwidth switches designed for either PCIe 3.0 or DisplayPort applications with a 7GHz or better bandwidth. However, these switches are intended to pass 4 data lines of traffic, not 5. If I route my MIPI clock or some data lane through another switch, and I only truly have 5ps of clock and data skew, there is absolutely no way I can meet that specification when factoring in PVT variations.

Some older devices that are 1.5Gbps parts report skew numbers in the 10s to 20s of ps range on their datasheet for inter-pair skew. Other newer devices, like the TS5MP646 intended for 2.5Gbps MIPI switching applications offer a 1ps typical intra-pair skew and 4ps inter-pair skew number.

I am surprised at the number of setups that “seem” to work with long (relatively speaking) harnessing (I-PEX CABLINE micro-coax) and multiple connectors; if all parties involved are truly splitting these specified margins between each PCB and harness, the traces must literally be routed with tolerances on the order of 10s of micrometers on length. Coupled with the fact that NVIDIA uses 90 ohms for their MIPI routing recommendation to optimize SI for their package / device while my camera vendor may have utilized 100 ohms and my harnessing is 100 ohms, I have no idea how this stuff is seemingly working with the published design margins at the published top speeds.

2

Hi kdesai,

  1. It is 350ps, this will be corrected, thanks.

  2. Yes, the skew between should be < 5ps. The skews are for 2.5Gbps, and the trace impedance of diff pair is 90-100 ohm, single end is 45-50 ohm.

The skew can be calculate with CAD tool during layout design, it will work well with presetting rules.

3

Hi Trumany,

Thanks for the confirmation. So utilizing a device like the TI TS5MP646 that has a typical lane-to-lane skew of 4ps would be considered to eat 80% of the skew margin if I wished to remain in specification?

What does that skew specification drop to for 1.5Gbps or slower speeds? I estimate the total bandwidth of my imager to be around 5.6Gbps without any overhead, and increasing to slightly over 6Gbps with protocol overhead. Can the CSI link be run at a slightly slower speed to gain back margin?

4

The skew is +/-5ps, so the 4ps skew of TS55MP646 might not eat 80% of the margin.

The skew is same for slower speed, as it is for alignment of intra/inter data/clock lines.

5

Ah, I did not realize it was a +/- number. I managed to find a copy of the D-PHY v1.2 specification and I see that in Table 30, it provides different skew numbers for 1.5Gbps and less vs. 2.5Gbps, defined in terms of the Unit Interval. For a 2.5Gbps D-PHY v1.2 link, is the UI 400ps?

That aside, it seems what you are saying is NVIDIA’s specification / guarantee of proper NVCSI functionality is as stated, a maximum of +/- 5ps data-to-clock skew. So, depending on the PVT of my specific signal switch and how it is defined, it could apply 4ps to all lanes, or it could apply -2ps to one land, +1ps to another lane, etc. all relative to my clock.

6

The inter-skew is DQ to CLK, the intra-skew is lane to lane in one pair, please follow the skew in OEM DG for all designs as it is validated by NV.