We are using a custom hardware to convert SDI-CSI2 and using that to interface with Jetson TX2 CSI port. By following Sensor programming guide I have modified the device tree and can see /dev/video0, however on trying to capture data using v4l2-ctl I am seeing syncpt error.
[ +0.999808] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ +1.002984] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ +1.002663] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ +1.005185] tegra-vi4 15700000.vi: ATOMP_FE syncpt timeout!
 TX2 is expecting Start of frame and timedout waiting for this. It could mean that data is not being received at TX2 end or not formatted correctly. Unfortunately I cannot probe on the lanes to check the data, are there any means with in the tegra vi driver to dump whatever is being received?
 We are using 4 data lanes connected to CSI4 and CSI5 on the Jetson board, which parameters in device-tree/tegra driver represent these values so that the SoC can read data from these ports?
I am using num_lanes = “4”, tegra_sinterface = “serial_a”, are these correct?
 Are there any specific set of registers that can be read to see if things are configured correctly?
 Any utilities/debugfs files to dump registers or read their values?