We are using a custom hardware to convert SDI-CSI2 and using that to interface with Jetson TX2 CSI port. By following Sensor programming guide I have modified the device tree and can see /dev/video0, however on trying to capture data using v4l2-ctl I am seeing syncpt error.
[1] TX2 is expecting Start of frame and timedout waiting for this. It could mean that data is not being received at TX2 end or not formatted correctly. Unfortunately I cannot probe on the lanes to check the data, are there any means with in the tegra vi driver to dump whatever is being received?
[2] We are using 4 data lanes connected to CSI4 and CSI5 on the Jetson board, which parameters in device-tree/tegra driver represent these values so that the SoC can read data from these ports?
I am using num_lanes = “4”, tegra_sinterface = “serial_a”, are these correct?
[3] Are there any specific set of registers that can be read to see if things are configured correctly?
[4] Any utilities/debugfs files to dump registers or read their values?
[1] The lanes value suggest that calibration is done only for CSIA, CSIB.
I am not sure whether these correspond to the lanes that we are using (CSI4, CSI5).
Could you please let me know how to check this?
[2] csi4_mipi_cal() in csi4_fops.c only uses lanes CSIA, CSIB - what about the other lanes (C~F)? Are they not required?
In summary, how does the channels CSI[0:5] on the carrier board correspond to channels CSI[A:F] referenced in the driver?
Regarding MIPI calibration - After going through the code I think it is clear to me now, previously csi-port=<0> because of which it was selecting lanes A, B.
I have changed csi-port=<4> and now I can see lanes E,F being selected but the PXL_SOF error is still there.
@asiluvery
From your tracing log tell CSI didn’t get any validate frame from the MIPI bus.
You can check the VI notify when you get some others message from the trace.