tx2 - Camera mipi timing and PXL_SOF

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

hello, nvidia friends,

	Before post the issue , I 've done search the forum for all PXl_SOF  and mipi issues, and tried all methods mentioned in post ,

but without positive results for two weeks, so your help and guidance is important will really helpful and appreciated.

  • [Hardware link]
    Tegra tx2 with ar0144 two camera sensor boards. configured wiht 1 csi lane per sensor. 
	DTSI part as below 

mode0 { // OV5693_MODE_2592X1944
				mclk_khz = "27000";
				num_lanes = "1";
				tegra_sinterface = "serial_a";
				discontinuous_clk = "no";
				dpcm_enable = "false";
				cil_settletime = "0";

				active_w = "1280";
				active_h = "720";
				pixel_t = "bayer_bggr12";
				readout_orientation = "90";
				line_length = "1488";
				inherent_gain = "1";
				mclk_multiplier = "2.75";
				pix_clk_hz = "74250000";

				min_gain_val = "1.0";
				max_gain_val = "16";
				min_hdr_ratio = "1";
				max_hdr_ratio = "64";
				min_framerate = "1.816577";
				max_framerate = "30";
				min_exp_time = "34";
				max_exp_time = "550385";
                		embedded_metadata_height = "0";
			};

[Issue logs]
kernel log as below :

[  108.806856] tegra-vi4 15700000.vi: Create Surface with imgW=1280, imgH=720, memFmt=32
[  108.816560] nvcsi 150c0000.nvcsi: csi port:0
[  109.318222] tegra_mipi_cal 3990000.mipical: Mipi cal timeout,val:208871, lanes:300000
[  109.326116] tegra_mipi_cal 3990000.mipical: MIPI_CAL_CTRL                  0x04 0x2a000010
[  109.334535] tegra_mipi_cal 3990000.mipical: CIL_MIPI_CAL_STATUS            0x0c 0x00208871
[  109.342881] tegra_mipi_cal 3990000.mipical: CIL_MIPI_CAL_STATUS_2          0x10 0x00000000
[  109.351222] tegra_mipi_cal 3990000.mipical: CILA_MIPI_CAL_CONFIG           0x18 0x00200000
[  109.359573] tegra_mipi_cal 3990000.mipical: CILB_MIPI_CAL_CONFIG           0x1c 0x00200000
[  109.367906] tegra_mipi_cal 3990000.mipical: CILC_MIPI_CAL_CONFIG           0x20 0x00000000
[  109.376207] tegra_mipi_cal 3990000.mipical: CILD_MIPI_CAL_CONFIG           0x24 0x00000000
[  109.384514] tegra_mipi_cal 3990000.mipical: CILE_MIPI_CAL_CONFIG           0x28 0x00000000
[  109.392825] tegra_mipi_cal 3990000.mipical: CILF_MIPI_CAL_CONFIG           0x2c 0x00000000
[  109.401127] tegra_mipi_cal 3990000.mipical: DSIA_MIPI_CAL_CONFIG           0x3c 0x00000200
[  109.409402] tegra_mipi_cal 3990000.mipical: DSIB_MIPI_CAL_CONFIG           0x40 0x00000200
[  109.417697] tegra_mipi_cal 3990000.mipical: DSIC_MIPI_CAL_CONFIG           0x44 0x00000200
[  109.425978] tegra_mipi_cal 3990000.mipical: DSID_MIPI_CAL_CONFIG           0x48 0x00000200
[  109.434262] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG0             0x5c 0x00000000
[  109.442547] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG1             0x60 0x00000000
[  109.450826] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG2             0x64 0x00010010
[  109.459110] tegra_mipi_cal 3990000.mipical: DSIA_MIPI_CAL_CONFIG_2         0x68 0x00000002
[  109.467405] tegra_mipi_cal 3990000.mipical: DSIB_MIPI_CAL_CONFIG_2         0x6c 0x00000002
[  109.475686] tegra_mipi_cal 3990000.mipical: DSIC_MIPI_CAL_CONFIG_2         0x74 0x00000002
[  109.483972] tegra_mipi_cal 3990000.mipical: DSID_MIPI_CAL_CONFIG_2         0x78 0x00000002
[  109.492256] nvcsi 150c0000.nvcsi: csi4_start_streaming ports index=0, lanes=1
[  109.499407] nvcsi 150c0000.nvcsi: csi4_stream_init
[  109.504231] nvcsi 150c0000.nvcsi: csi4_stream_config
[  109.509228] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[  109.517164] nvcsi 150c0000.nvcsi: csi4_phy_config
[  109.521890] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[  109.527638] nvcsi 150c0000.nvcsi: cil_a true
[  109.531916] nvcsi 150c0000.nvcsi: enable true in phy
[  109.536886] nvcsi 150c0000.nvcsi:  phy config end  cil core clock 204, csi clock 102
[  109.544629] ar0144 2-0010: ar0144_s_stream+++,enable=1,s_data->mode=0
[  109.551067]  our regmap_util_write_table_16_as_8:
[  109.556307] addr=301a,val=d9
[  109.579731] in sleep 20
[  109.582353] addr=3f4c,val=4b3f
[  109.585564] addr=3f4c,val=3f
[  109.588623] addr=3f4e,val=5718
[  109.591869] addr=3f4e,val=18
[  109.594918] addr=3f50,val=401f
[  109.598126] addr=3f50,val=17df
[  109.621730] in sleep 20
[  109.624387] addr=3ed6,val=3cb5
[  109.627641] addr=3ed8,val=8765
[  109.630872] addr=3eda,val=8888
[  109.634093] addr=3edc,val=97ff
[  109.637321] addr=3ef8,val=6522
[  109.640567] addr=3efa,val=2222
[  109.643807] addr=3efc,val=6666
[  109.647036] addr=3f00,val=aa05
[  109.650241] addr=3ee2,val=180e
[  109.653447] addr=3ee4,val=808
[  109.656576] addr=3eea,val=2a09
[  109.659793] addr=3060,val=d
[  109.662748] addr=3092,val=cf
[  109.665782] addr=3268,val=30
[  109.668825] addr=3786,val=6
[  109.671780] addr=3f4a,val=f70
[  109.674907] addr=306e,val=4810
[  109.678113] addr=3064,val=1802
[  109.681330] addr=3ef6,val=804d
[  109.684546] addr=3180,val=c08f
[  109.687760] addr=30ba,val=7623
[  109.690976] addr=3176,val=480
[  109.694096] addr=3178,val=480
[  109.697225] addr=317a,val=480
[  109.700354] addr=317c,val=480
[  109.703482] addr=302a,val=6
[  109.706437] addr=302c,val=2
[  109.709382] addr=302e,val=4
[  109.712339] addr=3030,val=42
[  109.715381] addr=3036,val=c
[  109.718336] addr=3038,val=1
[  109.721282] addr=30b0,val=38
[  109.744700] in sleep 20
[  109.747312] addr=31b0,val=2f
[  109.750367] addr=31b2,val=1c
[  109.753402] addr=31b4,val=1665
[  109.756629] addr=31b6,val=110e
[  109.759865] addr=31b8,val=2047
[  109.763082] addr=31ba,val=105
[  109.766202] addr=31bc,val=8004
[  109.769409] addr=31ae,val=201
[  109.772538] addr=3002,val=28
[  109.775580] addr=3004,val=4
[  109.778542] addr=3006,val=2f7
[  109.781661] addr=3008,val=503
[  109.784791] addr=300a,val=33b
[  109.787921] addr=300c,val=5d0
[  109.791047] addr=3012,val=33a
[  109.794176] addr=31ac,val=c0c
[  109.797305] addr=306e,val=9010
[  109.800521] addr=30a2,val=1
[  109.803477] addr=30a6,val=1
[  109.806431] addr=3082,val=3
[  109.809377] addr=3084,val=3
[  109.812331] addr=308c,val=28
[  109.815372] addr=308a,val=4
[  109.818327] addr=3090,val=2f7
[  109.821447] addr=308e,val=503
[  109.824577] addr=30aa,val=2eb
[  109.827705] addr=303e,val=5d0
[  109.830833] addr=3016,val=2ea
[  109.833953] addr=30ae,val=1
[  109.836906] addr=30a8,val=1
[  109.839863] addr=3040,val=0
[  109.842818] addr=31d0,val=1
[  109.845766] addr=301a,val=5c
[  109.848652] in read reg
[  109.851298] in read reg
[  109.853937] ar0144 2-0010: 0x31AC=c0c,0x31AE=201
[  109.858563] ar0144 2-0010: ar0144_s_stream--
[  109.909645] tegra-vi4 15700000.vi: Status:  2 channel:00 frame:0001
[  109.915916] tegra-vi4 15700000.vi:          timestamp sof 119499334016 eof 119527974912 data 0x00400060
[  109.925323] tegra-vi4 15700000.vi:          capture_id 1 stream  0 vchan  0
VIDIOC_DQBUF: failed: Input/output error
[  110.878218] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[  111.882227] tegra-vi4 15700000.vi: ATOMP_FE syncpt timeout!
[  111.888185] ar0144 2-0010: ar0144_s_stream+++,enable=0,s_data->mode=0
[  111.895026] in wirte reg
[  111.897825] nvcsi 150c0000.nvcsi: csi4_stop_streaming ports index=0, lanes=1
[  111.904922] nvcsi 150c0000.nvcsi: csi4_phy_config
[  111.909714] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000001
[  111.915541] nvcsi 150c0000.nvcsi: cil_a true
[  111.919938] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[  111.925546] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x00000004
[  111.933444] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x00000004
[  111.941673] nvcsi 150c0000.nvcsi: csi4_cil_check_status 284

Tracing logs as below :

kworker/5:2-280   [005] ...1   108.818221: rtos_queue_peek_from_isr_failed: tstamp:3700783005 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   108.818225: rtcpu_start: tstamp:3700783867
     kworker/5:2-280   [005] ...1   108.974190: rtos_queue_peek_from_isr_failed: tstamp:3705783867 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   109.130189: rtos_queue_peek_from_isr_failed: tstamp:3710784371 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   109.346174: rtos_queue_peek_from_isr_failed: tstamp:3715784877 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   109.454146: rtos_queue_peek_from_isr_failed: tstamp:3720785386 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   109.610175: rtos_queue_peek_from_isr_failed: tstamp:3725785872 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   109.822139: rtos_queue_peek_from_isr_failed: tstamp:3730786381 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   109.922148: rtcpu_vinotify_handle_msg: tstamp:3734354746 tag:CHANSEL_PXL_SOF channel:0x00 frame:1 vi_tstamp:3734354188 data:0x00000001
     kworker/5:2-280   [005] ...1   109.922150: rtcpu_vinotify_handle_msg: tstamp:3734354894 tag:ATOMP_FS channel:0x00 frame:1 vi_tstamp:3734354208 data:0x00000000
     kworker/5:2-280   [005] ...1   109.922150: rtcpu_vinotify_handle_msg: tstamp:3734357018 tag:CHANSEL_LOAD_FRAMED channel:0x01 frame:1 vi_tstamp:3734356605 data:0x08000000
     kworker/5:2-280   [005] ...1   109.922151: rtcpu_vinotify_handle_msg: tstamp:3735249906 tag:CHANSEL_PXL_EOF channel:0x00 frame:1 vi_tstamp:3735249193 data:0x02cf0002
     kworker/5:2-280   [005] ...1   109.922152: rtcpu_vinotify_handle_msg: tstamp:3735250010 tag:CSIMUX_FRAME channel:0x00 frame:1 vi_tstamp:3735249216 data:0x00400060
     kworker/5:2-280   [005] ...1   109.922153: rtcpu_vinotify_handle_msg: tstamp:3735250190 tag:ATOMP_FE channel:0x00 frame:1 vi_tstamp:3735249219 data:0x00000000
     kworker/5:2-280   [005] ...1   109.974160: rtos_queue_peek_from_isr_failed: tstamp:3735786885 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   110.130186: rtos_queue_peek_from_isr_failed: tstamp:3740787412 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   110.286184: rtos_queue_peek_from_isr_failed: tstamp:3745787921 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   110.442185: rtos_queue_peek_from_isr_failed: tstamp:3750788423 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   110.598184: rtos_queue_peek_from_isr_failed: tstamp:3755788933 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   110.754196: rtos_queue_peek_from_isr_failed: tstamp:3760789437 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   110.910175: rtos_queue_peek_from_isr_failed: tstamp:3765789933 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   111.066198: rtos_queue_peek_from_isr_failed: tstamp:3770790459 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   111.222195: rtos_queue_peek_from_isr_failed: tstamp:3775790959 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   111.378187: rtos_queue_peek_from_isr_failed: tstamp:3780791467 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   111.534195: rtos_queue_peek_from_isr_failed: tstamp:3785791971 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   111.690187: rtos_queue_peek_from_isr_failed: tstamp:3790792480 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   111.898238: rtos_queue_peek_from_isr_failed: tstamp:3795792985 queue:0x0b4a3c58
     kworker/5:2-280   [005] ...1   111.898246: rtos_queue_peek_from_isr_failed: tstamp:3797077929 queue:0x0b4a3c58
  • [Analysis]
kworker/5:2-280   [005] ...1   109.922148: rtcpu_vinotify_handle_msg: tstamp:3734354746 tag:CHANSEL_PXL_SOF channel:0x00 frame:1 vi_tstamp:3734354188 data:0x00000001
 kworker/5:2-280   [005] ...1   109.922150: rtcpu_vinotify_handle_msg: tstamp:3734354894 tag:ATOMP_FS channel:0x00 frame:1 vi_tstamp:3734354208 data:0x00000000
 kworker/5:2-280   [005] ...1   109.922150: rtcpu_vinotify_handle_msg: tstamp:3734357018 tag:CHANSEL_LOAD_FRAMED channel:0x01 frame:1 vi_tstamp:3734356605 data:0x08000000
 kworker/5:2-280   [005] ...1   109.922151: rtcpu_vinotify_handle_msg: tstamp:3735249906 tag:CHANSEL_PXL_EOF channel:0x00 frame:1 vi_tstamp:3735249193 data:0x02cf0002
 kworker/5:2-280   [005] ...1   109.922152: rtcpu_vinotify_handle_msg: tstamp:3735250010 tag:CSIMUX_FRAME channel:0x00 frame:1 vi_tstamp:3735249216 data:0x00400060
 kworker/5:2-280   [005] ...1   109.922153: rtcpu_vinotify_handle_msg: tstamp:3735250190 tag:ATOMP_FE channel:0x00 frame:1 vi_tstamp:3735249219 data:0x00000000

<b> These part seems correct , but not sure why just one frame we received ATOMP_FE,</b>

[ 111.919938] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 111.925546] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x00000004
[ 111.933444] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x00000004

Seems this(0x4) means crc correction error. No idea why this happen , mipi timing ?

  • [What I 've done]
1. Embeded meta lines settings. The sensor could be configured with 2 or without embeded meta lins. If I configured the sensor with embeded data lines and

2 in dtsi files, the result is the same.

2. Ths-settle and clk settle.

   From the calculation , our input is 1280x720x30 fps, I calculated and set it corresponding, not work. 
	UI_time = 2.1 ns 
	85ns + 6 * 2ns < (x+ 6) * 4.9ns < 145ns + 10 * 2ns
	so x= 0x16(22) fulfill the requirement. Actually , I tried values from 0 ~ 0x3F , all not work.

  For clk-settle, we got some values from sensor provider, in ns,
  
  Tclk_pre       17.9573, 
  Tclk_post      176.723,
  Tclk_prepare   38~95,
  Tclk_zero      300
  Tclk_trail  60 ,
  
  Not sure what will be the exact definition of clk_settle here , from mipi protocal , I assume it shall be Tclk_zero or Tclk_prepare + Tclk_zero, 
so I modify the value accordingly. But the result is not positive. Acutally , I also tried values from 0 ~0x5E, none successul 
  		
3. The output from tx1 is correct. I the difference seems tx1 mipi clock is 102MHz, tx2 is 204MHz, I tried values according to this differences , seems no good result.
2

Reference to this link. You can have comment to get the kernel driver to reference.

https://devtalk.nvidia.com/default/topic/1035385

3

Could you try discontinuous_clk = “yes”;

4

Shane, this is another issue not the previous one, the previous one is fixed by modify dtsi file , this is PXL_SOF
issue . Can you help to identify some direction ? I 've tried all comibination of ths-settle or clk-settle .

5

set discontinous_clk have the same result .

6

Does v4l2-ctl working well?

7

Nope , this is the v4l2-ctl result.

On tx1 it works well , but on tx2 it is not. I searched through the forum on PIX_SOF issue , and tried all methods mentioned in post.

8

CRC issue is a common issue, it can be caused by:
• Sensor TX side send bad pixe/crc value.
• SI quality of the CSI channel.

9

Below patch to disable payload CRC error check. And this sensor need modify embedded_metadata_height = “4”;
After this the v4l2-ctl should be able capture well.

diff --git a/drivers/media/platform/tegra/camera/csi/csi4_fops.c b/drivers/media/platform/tegra/camera/csi/csi4_fops.c
index 0377d7b..b3d01d3 100644
--- a/drivers/media/platform/tegra/camera/csi/csi4_fops.c
+++ b/drivers/media/platform/tegra/camera/csi/csi4_fops.c
@@ -76,8 +76,18 @@ static void csi4_stream_init(struct tegra_csi_channel *chan, int port_num)
        csi4_stream_write(chan, port_num, INTR_STATUS, 0x3ffff);
        csi4_stream_write(chan, port_num, ERR_INTR_STATUS, 0x7ffff);
        csi4_stream_write(chan, port_num, ERROR_STATUS2VI_MASK, 0x0);
-       csi4_stream_write(chan, port_num, INTR_MASK, 0x0);
-       csi4_stream_write(chan, port_num, ERR_INTR_MASK, 0x0);
+//     csi4_stream_write(chan, port_num, INTR_MASK, 0x0);
+//     csi4_stream_write(chan, port_num, ERR_INTR_MASK, 0x0);
+
+       csi4_stream_write(chan, port_num, INTR_MASK, PH_ECC_MULTI_BIT_ERR |
+                       PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
+       csi4_stream_write(chan, port_num, ERR_INTR_MASK, PH_ECC_MULTI_BIT_ERR |
+                       PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
+       csi4_stream_write(chan, port_num, ERROR_STATUS2VI_MASK,
+                       CFG_ERR_STATUS2VI_MASK_VC0 |
+                       CFG_ERR_STATUS2VI_MASK_VC1 |
+                       CFG_ERR_STATUS2VI_MASK_VC2 |
+                       CFG_ERR_STATUS2VI_MASK_VC3);
 }
10

Still no luck, the result is full of

[ 34.746302] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11.

We tried different embedded_metadata_height = 0 , 1,2,4 . Actually , from the sensor data sheet, the default
value will be 2 lines in the head and 2 lines in the tail . But if we disable or enable it , and with all
combinations of embedded_metadata_height . The result all have syncpt timeout.

The same code and config behaves well in tx1.

11

Does the trace still show CSIMUX_FRAME?

CSIMUX_FRAME channel:0x00 frame:1 vi_tstamp:3735249216 data:0x00400060

12

The trace as below.

kworker/0:2-287   [000] ...1    58.006268: rtcpu_vinotify_handle_msg: tstamp:2144938002 tag:ATOMP_FS channel:0x00 frame
:1 vi_tstamp:2144937588 data:0x00000000
     kworker/0:2-287   [000] ...1    58.006270: rtcpu_vinotify_handle_msg: tstamp:2144940489 tag:CHANSEL_PXL_SOF channel:0x0
0 frame:1 vi_tstamp:2144940045 data:0x00000001
     kworker/0:2-287   [000] ...1    58.006271: rtcpu_vinotify_handle_msg: tstamp:2144943165 tag:CHANSEL_LOAD_FRAMED channel
:0x04 frame:1 vi_tstamp:2144942757 data:0x08000000
     kworker/0:2-287   [000] ...1    58.058273: rtcpu_vinotify_handle_msg: tstamp:2145935231 tag:CHANSEL_PXL_EOF channel:0x0
0 frame:1 vi_tstamp:2145934516 data:0x031f0002
     kworker/0:2-287   [000] ...1    58.058276: rtcpu_vinotify_handle_msg: tstamp:2145935335 tag:CSIMUX_FRAME channel:0x00 f
rame:1 vi_tstamp:2145934539 data:0x00400062
     kworker/0:2-287   [000] ...1    58.058277: rtcpu_vinotify_handle_msg: tstamp:2145935524 tag:ATOMP_FE channel:0x00 frame
:1 vi_tstamp:2145934543 data:0x00000000
13

Still report the crc error looks like the crc mask didn’t set.
Have a read and print out those message to check.

14

Just ensure the crc mask work and device tree ok.
Now there is no syncpt timeout error , following is the trace

:1 vi_tstamp:4279367488 data:0x00000000
     kworker/3:1-53    [003] ...1   126.279631: rtcpu_vinotify_handle_msg: tstamp:4279370377 tag:CHANSEL_PXL_SOF channel:0x0
0 frame:1 vi_tstamp:4279369946 data:0x00000001
     kworker/3:1-53    [003] ...1   126.279632: rtcpu_vinotify_handle_msg: tstamp:4279373038 tag:CHANSEL_LOAD_FRAMED channel
:0x04 frame:1 vi_tstamp:4279372630 data:0x08000000
     kworker/3:1-53    [003] ...1   126.331638: rtcpu_vinotify_handle_msg: tstamp:4280365005 tag:CHANSEL_PXL_EOF channel:0x0
0 frame:1 vi_tstamp:4280364417 data:0x031f0002
     kworker/3:1-53    [003] ...1   126.331643: rtcpu_vinotify_handle_msg: tstamp:4280365109 tag:ATOMP_FE channel:0x00 frame
:1 vi_tstamp:4280364443 data:0x00000000
     kworker/3:1-53    [003] ...1   126.331646: rtcpu_vinotify_handle_msg: tstamp:4280402347 tag:ATOMP_FS channel:0x00 frame
:2 vi_tstamp:4280401928 data:0x00000000
     kworker/3:1-53    [003] ...1   126.331649: rtcpu_vinotify_handle_msg: tstamp:4280404803 tag:CHANSEL_PXL_SOF channel:0x0
0 frame:2 vi_tstamp:4280404386 data:0x00000001
     kworker/3:1-53    [003] ...1   126.331651: rtcpu_vinotify_handle_msg: tstamp:4280407201 tag:CHANSEL_LOAD_FRAMED channel
:0x04 frame:2 vi_tstamp:4280406792 data:0x08000000
     kworker/3:1-53    [003] ...1   126.331656: rtos_queue_peek_from_isr_failed: tstamp:4280982166 queue:0x0b4a3c58
     kworker/3:1-53    [003] ...1   126.383595: rtcpu_vinotify_handle_msg: tstamp:4281399471 tag:CHANSEL_PXL_EOF channel:0x0
0 frame:2 vi_tstamp:4281398857 data:0x031f0002
     kworker/3:1-53    [003] ...1   126.383603: rtcpu_vinotify_handle_msg: tstamp:4281399613 tag:ATOMP_FE channel:0x00 frame
:2 vi_tstamp:4281398883 data:0x00000000
     kworker/3:1-53    [003] ...1   126.383605: rtcpu_vinotify_handle_msg: tstamp:4281436809 tag:ATOMP_FS channel:0x00 frame
:3 vi_tstamp:4281436369 data:0x00000000
     kworker/3:1-53    [003] ...1   126.383608: rtcpu_vinotify_handle_msg: tstamp:4281439263 tag:CHANSEL_PXL_SOF channel:0x0
0 frame:3 vi_tstamp:4281438826 data:0x00000001
     kworker/3:1-53    [003] ...1   126.383611: rtcpu_vinotify_handle_msg: tstamp:4281443484 tag:CHANSEL_LOAD_FRAMED channel
:0x04 frame:3 vi_tstamp:4281443058 data:0x08000000
     kworker/3:1-53    [003] ...1   126.383613: rtcpu_vinotify_handle_msg: tstamp:4282433902 tag:CHANSEL_PXL_EOF channel:0x0
0 frame:3 vi_tstamp:4282433297 data:0x031f0002
     kworker/3:1-53    [003] ...1   126.383616: rtcpu_vinotify_handle_msg: tstamp:4282434039 tag:ATOMP_FE channel:0x00 frame
:3 vi_tstamp:4282433323 data:0x00000000
     kworker/3:1-53    [003] ...1   126.383619: rtcpu_vinotify_handle_msg: tstamp:4282471247 tag:ATOMP_FS channel:0x00 frame
:4 vi_tstamp:4282470809 data:0x00000000
     kworker/3:1-53    [003] ...1   126.383622: rtcpu_vinotify_handle_msg: tstamp:4282473707 tag:CHANSEL_PXL_SOF channel:0x0
0 frame:4 vi_tstamp:4282473266 data:0x00000001
     kworker/3:1-53    [003] ...1   126.383625: rtcpu_vinotify_handle_msg: tstamp:4282479238 tag:CHANSEL_LOAD_FRAMED channel
:0x04 frame:4 vi_tstamp:4282478809 data:0x08000000
     kworker/3:1-53    [003] ...1   126.435557: rtcpu_vinotify_handle_msg: tstamp:4283468344 tag:CHANSEL_PXL_EOF channel:0x0
0 frame:4 vi_tstamp:4283467736 data:0x031f0002
     kworker/3:1-53    [003] ...1   126.435561: rtcpu_vinotify_handle_msg: tstamp:4283468484 tag:ATOMP_FE channel:0x00 frame
:4 vi_tstamp:4283467762 data:0x00000000

However, the raw captured only have a few lines in the top , and others all black. Possible cause ? The values in devices tree like pix_clk_hz, mclk_multiplier is the same that worked in tx1.

15

Could you try the color pattern.

16

I mean the raw data , not pass ISP pipe line, is whole black, it shall not related to the color pattern.

17

Yes, I know not pass to ISP however still please set the sensor output color pattern to verify.

18

We changed the color pattern values, there is no difference on the result.
The weird thing we found is that we can only set embedded_metadata_height = “1”, we could have
output image instead of all black, and on this case , there is still timeout log. And from the
sensor datasheet, current we shall have embedded_metadata_height = “2”, is correct.

19

My config is embedded_metadata_height = “4” there’s no problem for me.
Did you build this sensor by yourself or buy it from vendor?

20

Can you share me your mode table for the sensor ?
What is value for register 0x3064 , Set it or leave it as default. We build the sensor board ourself.