MIPI C-PHY data rate of TX2 and AGX Xavier

According to MIPI C-PHY v1.0 spec, Data rate per lane is max 2.5 Gsym/s (5.7 Gbps).


https://www.mipi.org/sites/default/files/PHY_Tech_Brief_20140916_0.pdf

but the spec in AGX Xavier datasheet is descried MIPI C-PHY v1.1, support up to 1.7 Gsym/s per trio.

We would like to know if TX2 and AGX Xavier can support 2.5 Gsym/s for C-PHY.

hello davidcoo882,

there’s no CPHY support for TX2 platforms.
may I know what’s your CPHY sensor data rate? thanks

We will test with SONY IMX586 which supports 2.5Gsym/s per Trio and totally up to three Trios. How about AGX Xavier? Can it support that?

[EDIT]

hello davidcoo882,

according to MIPI specification, 3-phase symbol encoding technology delivers approximately 2.28 bits-per-symbol.
hence, 2.28 bits/sym * 2.5 Gsym/s = 5.7 Gbps

also, according to Jetson AGX Xavier OEM Product Design Guide, for C-PHY, Xavier supports each lane (Trio) supports up to 2.5 Gsps.
the maximum data rate should be 5.715 (2.5x2.286) Gbps, which should be able to cover your request.

Please check comment #6 for correct CPHY data rate. thanks

Hi Jerry,

For AGX Xavier, please check “1.4.1 MIPI Camera Serial Interface (CSI)” section of AGX Xavier datasheet.

Features:
• Supports both the MIPI D-PHY v1.2 and the MIPI C-PHY v1.1 physical layer options.
MIPI D-PHY supports up to 2.5 Gbits/sec per pair, for an aggregate bandwidth of 40 Gbps from 16 pairs
MIPI C-PHY supports up to[b] 1.7 G symbol/sec /b per trio

For TX2, please refer to below link and you replied C-PHY is supported.
https://devtalk.nvidia.com/default/topic/1026852/does-tx2-bsp-support-mipi-csi-c-phy-/?offset=5#5304971

Hi, on Xavier, data rate of C-PHY is up to 1.7Gsym/s per trio. There is a doc issue of 2.5Gsysm/s per tiro supported in OEM DG which will be corrected. C-PHY is not supported on Jetson TX2 platform.

Hi Trumany,

Is it possible to tune up to 2.5Gsym/s or higher? This is very important for our future product plan.

David

No, 1.7Gsym/s is the limit of current module design.

Hi Trumany,
According to Xavier TRM V1.3p which revised on 20191004.
In Table 7.7, Peak bandwidth in C-PHY is changed from 109 (3.0 x 2.28 x 4 x 4) to 91 (2.5 x 2.28 x 4 x 4). That means the original design of C-PHY is 3Gs/s and TRM V1.3p modify it to 2.5Gs/s.

Moreover, in Table 7.10 System Lvel Peak Bandwidth, there are 3 PHY mode on C-PHY depending on different NVCSI clock and lane clock.
Target VLV LV SV
BW/Trio 1.68 Gs/s 2.0 Gs/s 3.0 Gs/s
Totaol BW 61 Gbps 73 Gbps 109 Gps
Lane clock 240MHz 286 MHz 428.6 MHz
NVCSI clock 240MHz 314 MHz 428.6 MHz

I have two questions:

  1. Looks like Xavier could only run VLV mode, what causes the limitation? NVCSI, VI or other issue?
  2. NVCSI clock is adjustable and I can modify it but I can’t find where to set Lane clock. Coudl you show me how to set lane clock?

TRM is for chip level, some features are not implemented on Jetson platform for some reasons. Please take module datasheet and OEM DG as spec and so not try to set NVCSI clock manually.

Hello
Did you manage to interface the IMX586 to the nvidia platform ?
Thanks a lot
Jean-Pierre

Hi Jean-Pierre,

Actually I don’t have IMX586 sample for test but I know it can be configed as C-PHY.

David